US5778440A — Floating gate memory device and method for termin…

Claim 1

Independent Claim 109 words

An integrated circuit memory, comprising: an array of storage elements; input/output circuitry, having inputs to receive addresses and data and coupled to the array, to read and store data segments in the array in response to the addresses and the data on the inputs; and command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and the data received at the input/output circuitry.

Claim 2

Dependent Claim 109 words

An integrated circuit memory, comprising: an array of storage elements; input/output circuitry, having inputs to receive addresses and data and coupled to the array, to read and store data segments in the array in response to the addresses and the data on the inputs; and command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and the data received at the input/output circuitry.

Claim 3

Dependent Claim 36 words

The memory of claim 1, wherein the pattern includes consecutive matching addresses, and the command logic includes a store for an address and a comparator to compare a received address with the address in the store.

Claim 4

Dependent Claim 54 words

The memory of claim 1, wherein the pattern includes consecutive matching addresses and consecutive matching data segments, and the command logic includes a store for an address and a data segment and a comparator to compare a received address and a received data segment with an address and a data segment in the store.

Claim 5

Dependent Claim 60 words

The memory of claim 1, wherein locations for data to be stored in the array are identified by addresses within an address range, and the pattern includes a command address outside the address range, and the command logic includes a store for the command address and a comparator to match a received address with the command address in the store.

Claim 6

Dependent Claim 82 words

The memory of claim 1, wherein locations for data to be stored in the array are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a high order segment and a low order segment, and the pattern includes a start command, supplied in the high order segment, comprising a bit pattern outside the address range, supplied after loading of the block of data into the array of storage elements.

Claim 7

Dependent Claim 82 words

The memory of claim 1, wherein locations for data to be stored in the array are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a high order segment and a low order segment, and the pattern includes a load command, supplied in the high order segment, comprising a bit pattern outside the address range, supplied during loading of the block of data into the array of storage elements.

Claim 8

Dependent Claim 38 words

The memory of claim 6, wherein the pattern includes changing the high order segment of the received address from the load command to the value within the address range while loading a last data segment in the sequence.

Claim 9

Dependent Claim 13 words

The memory of claim 1, wherein the array comprises floating gate memory cells.

Claim 10

Dependent Claim 33 words

The memory of claim 1, wherein the command logic includes a state machine which automatically programs and verifies programming of the block of data after the last segment in the block is detected.

Claim 11

Dependent Claim 46 words

The memory of claim 1, wherein the array comprises floating gate memory cells, and the input/output circuitry includes a state machine, responsive to the command logic, which automatically programs and verifies programming of the block of data after the last segment in the block is detected.

Claim 12

Dependent Claim 35 words

The memory of claim 10, wherein the input/output circuitry includes program/erase voltage sources coupled to the state machine which apply potentials to the floating gate cells which cause Fowler-Nordheim tunneling in cells to be programmed.

Claim 13

Dependent Claim 36 words

The memory of claim 10, wherein the input/output circuitry includes program/erase voltage sources coupled to the state machine which apply potentials to the floating gate cells which cause hot electron injection in cells to be programmed.

Claim 14

Dependent Claim 82 words

The memory of claim 1, wherein the input/output circuitry receives a control signal establishing timing for the sequence of addresses and data segments, the command logic includes logic to detect a pulse in the control signal having a characteristic pulse width indicating that the block is loaded, wherein the logic includes a state machine, responsive to the command logic, which automatically programs and verifies programming of the block of data after the last segment in the block or the pulse is detected.

Claim 15

Dependent Claim 25 words

The memory of claim 1, wherein the pattern comprises an address transition in the sequence of addresses and data segments received at the input/output circuitry.

Claim 16

Dependent Claim 258 words

A floating gate memory circuit on a semiconductor substrate comprising: a memory array including at least M rows and N columns of floating gate cells; M word lines, each coupled to the floating gate cells in one of the M rows of floating gate cells; a plurality of bit lines, each coupled to the floating gate cells in at least one of the N columns of floating gate cells; input/output circuitry, having inputs to receive addresses and data; command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and data received at the input/output circuitry; a page buffer, coupled to the input/output circuitry to store the block of data and supply the block of data to the N columns of floating gate cells; write control circuitry, coupled to the command logic, the page buffer and the M word lines, which after detection of the last segment in the block, supplies programming voltages to a selected word line for programming input data to a row of floating gate cells accessed by the selected word line in response to the block of data stored in the page buffer; and program verify circuitry, coupled to the page buffer, which verifies that floating gate cells are programmed with the block of data in the page buffer.

Claim 17

Dependent Claim 258 words

A floating gate memory circuit on a semiconductor substrate comprising: a memory array including at least M rows and N columns of floating gate cells; M word lines, each coupled to the floating gate cells in one of the M rows of floating gate cells; a plurality of bit lines, each coupled to the floating gate cells in at least one of the N columns of floating gate cells; input/output circuitry, having inputs to receive addresses and data; command logic, coupled to the input/output circuitry, which executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, including logic to detect a last segment of the block of data in response to a pattern including at least one of the addresses and data received at the input/output circuitry; a page buffer, coupled to the input/output circuitry to store the block of data and supply the block of data to the N columns of floating gate cells; write control circuitry, coupled to the command logic, the page buffer and the M word lines, which after detection of the last segment in the block, supplies programming voltages to a selected word line for programming input data to a row of floating gate cells accessed by the selected word line in response to the block of data stored in the page buffer; and program verify circuitry, coupled to the page buffer, which verifies that floating gate cells are programmed with the block of data in the page buffer.

Claim 18

Dependent Claim 65 words

The floating gate memory circuit of claim 15, wherein the page buffer includes a plurality of bit latches coupled to corresponding ones of the plurality of bit lines, and the program verify circuitry, coupled to the bit lines, resets a bit latch to a first binary value when stored data in a floating gate cell on a corresponding bit line matches a second binary value.

Claim 19

Dependent Claim 48 words

The floating gate memory circuit of claim 15, wherein: a row of N columns of floating gate cells includes a first page of floating gate cells and a second page of floating gate cells; and the page buffer supplies input data to a page of floating gate cells.

Claim 20

Dependent Claim 46 words

The floating gate memory circuit of claim 16, wherein the program verify circuitry includes logic responsive to stored data from the floating gate cells and to data in the page buffer to provide a program verify signal when all programmed floating gate cells pass program verify.

Claim 21

Dependent Claim 27 words

The floating gate memory circuit of claim 16, wherein the program verify circuitry generates a program verify signal when all bit latches store the first binary value.

Claim 22

Dependent Claim 50 words

The floating gate memory circuit of claim 19, wherein the write control circuitry applies a word line program potential to a word line coupled to a selected set of floating gate cells, and a bit line program potential to bit lines coupled to bit latches storing the second binary value.

Claim 23

Dependent Claim 54 words

The floating gate memory circuit of claim 15, wherein the pattern includes consecutive matching addresses, and the command logic includes a store, coupled to the input/output circuitry, to hold an address and a comparator, coupled to the input/output circuitry, to compare a currently received address with a previously received address held in the store.

Claim 24

Dependent Claim 69 words

The floating gate memory circuit of claim 15, wherein the pattern includes consecutive matching addresses and consecutive matching data segments, and the command logic includes a store, coupled to the input/output circuitry, to hold an address and a data segment and a comparator, coupled to the input/output circuitry, to compare a currently received address and data segment with a previously received address and data segment held in the store.

Claim 25

Dependent Claim 63 words

The floating gate memory circuit of claim 15, wherein locations in the array are identified by addresses within an address range, and the pattern includes a command address outside the address range, and the command logic includes a store for the command address and a comparator, coupled to the input/output circuitry, to compare a received address with the command address in the store.

Claim 26

Dependent Claim 81 words

The floating gate memory circuit of claim 15, wherein locations for data to be stored are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a page address segment and a page buffer address segment, and the pattern includes a start command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied after loading of the block of data into the memory array.

Claim 27

Dependent Claim 81 words

The floating gate memory circuit of claim 15, wherein locations for data to be stored are identified by addresses received on the inputs of the input/output circuitry within an address range, the addresses within the address range having a page address segment and a page buffer address segment, and the pattern includes a load command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied during loading of the block of data into the memory array.

Claim 28

Dependent Claim 41 words

The floating gate memory circuit of claim 25, wherein the pattern includes changing the page address segment of the received address from the load command to the value within the address range while loading a last data segment in the sequence.

Claim 29

Dependent Claim 76 words

The floating gate memory circuit of claim 15, wherein the input/output circuitry receives a control signal establishing timing for the sequence of addresses and data segments, the command logic includes logic to detect a pulse in the control signal having a characteristic pulse width indicating that the block is loaded, and wherein the write control circuitry applies program voltages in response to either detection of the last segment in the block or detection of the pulse.

Claim 30

Dependent Claim 26 words

The floating gate memory circuit of claim 15, wherein the programming voltages applied to the floating gate cells cause Fowler-Nordheim tunneling in cells to be programmed.

Claim 31

Dependent Claim 27 words

The floating gate memory circuit of claim 15, wherein the programming voltages applied to the floating gate cells cause hot electron injection in cells to be programmed.

Claim 32

Dependent Claim 27 words

The floating gate memory of claim 15, wherein the pattern comprises an address transition in the sequence of addresses and data segments received at the input/output circuitry.

Claim 33

Independent Claim 112 words

A method for storing a block of data consisting of less than or equal to a page in a floating gate memory device, comprising: supplying a command which indicates an automatic program operation to the memory device; after supplying the command, supplying a stream of addresses and segments of data, and storing the supplied segments in a page buffer; monitoring the supplied stream of addresses and segments of data to detect a pattern in the supplied stream which signals an end of the block of data; and after detection of the pattern, executing a program operation to store the block of data from the page buffer into the floating gate memory device.

Claim 34

Independent Claim 112 words

A method for storing a block of data consisting of less than or equal to a page in a floating gate memory device, comprising: supplying a command which indicates an automatic program operation to the memory device; after supplying the command, supplying a stream of addresses and segments of data, and storing the supplied segments in a page buffer; monitoring the supplied stream of addresses and segments of data to detect a pattern in the supplied stream which signals an end of the block of data; and after detection of the pattern, executing a program operation to store the block of data from the page buffer into the floating gate memory device.

Claim 35

Dependent Claim 17 words

The method of claim 31, wherein the pattern includes two matching addresses in sequence in the stream.

Claim 36

Dependent Claim 24 words

The method of claim 31, wherein the pattern includes a sequence of two matching addresses and two matching segments of data in the system.

Claim 37

Dependent Claim 19 words

The method of claim 31, wherein the pattern includes an address in the stream matching a prespecified command address.

Claim 38

Dependent Claim 82 words

The method of claim 31, wherein locations in the floating gate memory device for data to be stored are identified by the stream of addresses within an address range, the stream of addresses within the address range having a page address segment and a page buffer address segment, and the pattern includes a start command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied after loading the block of data into the floating gate memory device.

Claim 39

Dependent Claim 100 words

The method of claim 31, wherein locations in the floating gate memory device for data to be stored are identified by the stream of addresses within and address range, the stream of addresses within the address range having a page address segment and a page buffer segment, and the pattern includes a load command, supplied in the page address segment, comprising a bit pattern outside the address range, supplied during loading of the block of data into the floating gate memory device, the pattern further including a change in the page address segment to a value within the address range.

Claim 40

Dependent Claim 38 words

The method of claim 36, wherein the pattern includes changing the page address segment of the received address from the load command to the value within the address range while loading a last data segment in the stream.

Claim 41

Dependent Claim 18 words

The method of claim 31, wherein the step of storing includes storing the block of data in parallel.

Claim 42

Dependent Claim 34 words

The method of claim 31, further including the step of automatically verifying the storing of the block of data into the floating gate memory device, and retrying the storing if an error is found.

Claim 43

Dependent Claim 21 words

The method of claim 31, wherein the pattern comprises an address transition in the stream of supplied addresses and data segments.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-07-06	2002-01-05	2002-07-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-07-06	2006-01-05	2006-07-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-07-06	2010-01-05	2010-07-07	$7700.00	Window Closed / Lapsed

Floating gate memory device and method for terminating a program load cycle upon detecting a predetermined address/data pattern

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