Patent US5774015A successfully refreshed from Google Patents.
US5774015A
Expired / Lapsed
US
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Compact semiconductor integrated circuit capable of reducing electromagnetic emission
Assignee: NEC Corp
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Filing: 1995-12-14
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Granted: 1998-06-30
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Expires: 2015-12-14
Abstract
Abstract In a semiconductor integrated circuit for use in a signal processing, each of semiconductor elements contained in a region 101 is composed of a MOS transistor having a short channel length while each of semiconductor elements contained in a region 102 is composed of a MOS transistor having a long channel length. Although the semiconductor elements contained in the region 101 are rapidly operable with a short rising time and a short trailing time, those contained in the region 102 are operable comparatively slow with a long rising time and a long trailing time. Accordingly, it is possible to reduce electromagnetic emissions produced in the region 102.
Inventors
- 👤 Kouichi Murakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
95 words
A semiconductor integrated circuit comprising: a fast operation circuit which is operable at a primary operation speed and which is composed of a semiconductor element operable with a first rising time and a first trailing time; a slow operation circuit which is operable at a secondary operation speed smaller than said primary operation speed and which is composed of a semiconductor element operable with a second rising time and a second trailing time; and said second rising time and said second trailing time being longer than said first rising time and said first trailing time.
Claim 2
Dependent Claim
95 words
A semiconductor integrated circuit comprising: a fast operation circuit which is operable at a primary operation speed and which is composed of a semiconductor element operable with a first rising time and a first trailing time; a slow operation circuit which is operable at a secondary operation speed smaller than said primary operation speed and which is composed of a semiconductor element operable with a second rising time and a second trailing time; and said second rising time and said second trailing time being longer than said first rising time and said first trailing time.
Claim 3
Dependent Claim
53 words
A semiconductor integrated circuit as claimed in claim 1, said fast operation circuit being composed of a first MOS transistor having a first channel length, said slow operation circuit being composed of a second MOS transistor having a second channel length, wherein said second channel length is larger than said first channel length.
Claim 4
Dependent Claim
43 words
A semiconductor integrated circuit as claimed in claim 1, said fast operation circuit being supplied with a first bias voltage, said slow operation circuit being supplied with a second bias voltage, wherein said second bias voltage is lower than said first bias voltage.
Claim 5
Dependent Claim
53 words
A semiconductor integrated circuit as claimed in claim 1, said fast operation circuit being composed of a first semiconductor element having a first parasitic capacitance, said slow operation circuit being composed of a second semiconductor element having a second parasitic capacitance, wherein said second parasitic capacitance is larger than said first parasitic capacitance.
Claim 6
Dependent Claim
107 words
A semiconductor integrated circuit for use in a signal processing which includes serial-parallel conversion, comprising: a serial signal processing circuit which is operable at a primary operation speed and which is composed of a semiconductor element operable with a first rising time and a first trailing time; a parallel signal processing circuit which is operable at a secondary operation speed smaller than said primary operation speed and which is composed of a semiconductor element operable with a second rising time and a second trailing time; and said second rising time and said second trailing time being longer than said first rising time and said first trailing time.
Claim 7
Dependent Claim
107 words
A semiconductor integrated circuit for use in a signal processing which includes serial-parallel conversion, comprising: a serial signal processing circuit which is operable at a primary operation speed and which is composed of a semiconductor element operable with a first rising time and a first trailing time; a parallel signal processing circuit which is operable at a secondary operation speed smaller than said primary operation speed and which is composed of a semiconductor element operable with a second rising time and a second trailing time; and said second rising time and said second trailing time being longer than said first rising time and said first trailing time.
Claim 8
Dependent Claim
55 words
A semiconductor integrated circuit as claimed in claim 5, said serial signal processing circuit being composed of a first MOS transistor having a first channel length, said parallel signal processing circuit being composed of a second MOS transistor having a second channel length, wherein said second channel length is larger than said first channel length.
Claim 9
Dependent Claim
45 words
A semiconductor integrated circuit as claimed in claim 5, said serial signal processing circuit being supplied with a first bias voltage, said parallel signal processing circuit being supplied with a second bias voltage, wherein said second bias voltage is lower than said first bias voltage.
Claim 10
Dependent Claim
55 words
A semiconductor integrated circuit as claimed in claim 5, said serial signal processing circuit being composed of a first semiconductor element having a first parasitic capacitance, said parallel signal processing circuit being composed of a second semiconductor element having a second parasitic capacitance, wherein said second parasitic capacitance is larger than said first parasitic capacitance.
Claim 11
Dependent Claim
71 words
A semiconductor integrated circuit comprising: a semiconductor substrate having a central portion and an outer portion; a fast operation circuit which is composed of a first semiconductor element having a first parasitic capacitance; a slow operation circuit which is composed of a second semiconductor element having a second parasitic capacitance; said second semiconductor element being positioned at said central portion; and said first semiconductor element being positioned at said outer portion.
Claim 12
Dependent Claim
71 words
A semiconductor integrated circuit comprising: a semiconductor substrate having a central portion and an outer portion; a fast operation circuit which is composed of a first semiconductor element having a first parasitic capacitance; a slow operation circuit which is composed of a second semiconductor element having a second parasitic capacitance; said second semiconductor element being positioned at said central portion; and said first semiconductor element being positioned at said outer portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |