US4599522A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog switch circuit having output offset compensation circuit
Assignee: Toshiba Corp
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Filing: 1983-11-17
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Granted: 1986-07-08
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Expires: 2003-11-17
Abstract
Abstract An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances C mP12 , C mP13 , C mN12 , C mN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance C mN11 of the first n channel MOS transistor and the mirror capacitance C mP11 of the first p channel MOS transistor.
Inventors
- 👤 Kenji Matsuo
- 👤 Fuminari Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:05
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/06; H03K17/16; H03K17/161; H03K17/162; H03K17/6871; H03K17/6872
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
160 words
An analog switch circuit responsive to complementary control signals, said analog switch circuit comprising: a transmission gate comprising a first n channel MOS transistor and a first p channel MOS transistor which are connected in parallel to form first and second junctions, said first junction forming an input terminal and said second junction forming an output terminal, the gates of said first n and p channel MOS transistors each being connected to receive a respective one of said complementary control signals; and an output voltage compensation circuit comprising a second n channel MOS transistor and a second p channel MOS transistor whose gates are connected to said output terminal of said transmission gate, the drain and source of said second n channel MOS transistor being connected to said gate of said first p channel MOS transistor, and the drain and source of said second p channel MOS transistor being connected to said gate of said first n channel MOS transistor.
Claim 2
Dependent Claim
160 words
An analog switch circuit responsive to complementary control signals, said analog switch circuit comprising: a transmission gate comprising a first n channel MOS transistor and a first p channel MOS transistor which are connected in parallel to form first and second junctions, said first junction forming an input terminal and said second junction forming an output terminal, the gates of said first n and p channel MOS transistors each being connected to receive a respective one of said complementary control signals; and an output voltage compensation circuit comprising a second n channel MOS transistor and a second p channel MOS transistor whose gates are connected to said output terminal of said transmission gate, the drain and source of said second n channel MOS transistor being connected to said gate of said first p channel MOS transistor, and the drain and source of said second p channel MOS transistor being connected to said gate of said first n channel MOS transistor.
Claim 3
Dependent Claim
65 words
The analog switch circuit according to claim 1, wherein, when the channel widths of the first and second p channel MOS transistors are respectively denoted by W P11 , W P12 , and the channel widths of the first and second n channel MOS transistors are respectively represented by W N11 , W N12 , the following equations result: W.sub.P12 =W.sub.P11 /2 W.sub.N12 =W.sub.N11 /2
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-07 | 1990-01-06 | 1990-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-07 | 1994-01-06 | 1994-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-07 | 1998-01-06 | 1998-07-08 | $7700.00 | Window Closed / Lapsed |