Semiconductor transmission gate with capacitance compensation

Claim 2

Circuitry comprising: a first field effect transistor of a first conductivity type and having first and second output terminals and a gate terminal and having a first parasitic capacitance coupled between the gate terminal and the first output terminal and having a second parasitic capacitance coupled between the gate terminal and the second output terminal; first, second, third and fourth capacitance means each having first and second terminals; first and second inverters each having an input terminal and an output terminal; a first circuitry input/output terminal being coupled to the first terminals of the first and second capacitive means and to the first output terminal of the first transistor; a second circuitry input/output terminal being coupled to the first terminals of the third and fourth capacitive means and to the second output terminal of the first transistor; the second terminals of the first and third capacitive means being coupled to the input terminal of the first inverter; the output terminal of the first inverter being coupled to the input terminal of the second inverter and to the gate terminal of the first transistor; the output terminal of the second inverter being coupled to the second terminals of the second and fourth capacitive means; and the first and second capacitive means have approximately equal capacitances with the sum of the two being approximately equal to the capacitance of the first parasitic capacitance; and the third and fourth capacitive means have approximately equal capacitances with the sum of the two being approximately equal to the capacitance of the second parasitic capacitance.

Claim 3

The circuitry of claim 1 wherein each one of the first, second, third and fourth capacitive means is a separate field effect transistor having two output terminals and a control terminal with the first terminal of each capacitive means being the two output terminals of its corresponding transistor and the second terminal of each capacitive means being the control terminal of its corresponding transistor.

Claim 4

The circuitry of claim 2 wherein all the transistors are MOS transistors and each of the four transistors which form the first, second, third and fourth capacitive means has the same geometry as the first transistor except that the first transistor has a channel width which is four times as large as each of the other transistors.

Claim 5

The circuitry of claim 3 wherein the first transistor and the transistors which comprise the first, second, third and fourth capacitive means are all n-channel MOS transistors.

Claim 6

The circuitry of claim 3 wherein the first transistor and the transistors which comprise the first, second, third and fourth capacitive means are all p-channel MOS transistors.

Claim 7

The circuitry of claim 3 wherein the first transistor is of first conductivity type and the transistors which comprise the first, second third and fourth capacitive means are of the opposite conductivity type.

Claim 8

The circuitry of claim 1 further comprising: a second field effect transistor of a second conductivity type and having first and second output terminals and a control terminal and a third parasitic capacitance coupled between the control terminal and the first output terminal and having a fourth parasitic capacitance coupled between the control terminal and the second output terminal; the first and second transistors are both MOS transistors; fifth, sixth, seventh and eighth capacitance means each having first and second terminals; third and fourth inverters each having an input terminal and an output terminal; the first circuitry input/output terminal being coupled to the first terminals of the fifth and sixth capacitive means and to the first output terminal of the second transistor; the second circuitry input/output terminal being coupled to the first terminals of the seventh and eighth capacitive means and to the second output terminal of the second transistor; the second terminals of the fifth and seventh capacitive means being coupled to the input terminal of the third inverter; the output terminal of the third inverter being coupled to the input terminal of the fourth inverter and to the gate terminal of the second MOS transistor; the output terminal of the fourth inverter being coupled to the second terminals of the sixth and eighth capacitive means; the fifth and sixth capacitive means have approximately equal capacitances and the sum of the two being approximately equal to the capacitance of the third parasitic capacitance; and the seventh and eighth capacitive means have approximately equal capacitances and the sum of the two being approximately equal to the capacitance of the fourth parasitic capacitance; the first, second third and fourth capacitive means are each a separate MOS transistor with the first terminal of each capacitive means being the two output terminals of the transistor comprising same and the second terminal of each capacitive means being the gate terminal of the transistor comprising same; the fifth, sixth, seventh and eighth capacitive means are each a separate MOS transistor with the first terminal of each capacitive means being the two output terminals of the transistor comprising same and the second terminal of each capacitive means being the gate terminal of the transistor comprising same; the first transistor and each of the four transistors which comprise the first, second, third and fourth capacitive means have the same geometry except that the first transistor has a channel width which is four times as large as that of the other four transistors that form the first, second, third and fourth capacitance means; and the second transistor and each of the four transistors which comprise the fifth, sixth, seventh and eighth capacitive means have the same geometry except that the second transistor has a channel width which is four times as large as that of the other four transistors that form the fifth, sixth, seventh and eighth capacitance means.

Claim 9

The circuitry of claim 7 wherein: the first transistor and the transistors which comprise the first, second, third and fourth capacitive means are all n-channel MOS transistors; and the second transistor and the transistors which comprise the fifth, sixth, seventh and eighth capacitive means are all p-channel MOS transistors.

Claim 10

The circuitry of claim 7 wherein: the first transistor is an n-channel MOS transistor and the transistors which comprise the first, second, third and fourth capacitive means are all p-channel MOS transistors; and the second transistor is a p-channel MOS transistor and the transistors which comprise the fifth, sixth, seventh and eighth capacitive means are all n-channel MOS transistors.

Claim 11

A transmission gate comprising: a first MOS transistor of a first conductivity type and having a source, a drain and a gate and having a first parasitic capacitance coupled between the gate and drain, and having a second parasitic capacitance coupled between the gate and source; first, second, third and fourth capacitors each having first and second terminals; the second terminals of the first and second capacitors being coupled together and being coupled to the drain of the first MOS transistor; the second terminals of the third and fourth capacitors being coupled to the source of the first MOS transistor; means for applying a first control signal to the first terminals of the first and third capacitors, a delayed and inverted version of the first control signal to the gate of the first MOS transistor, and a further delayed version of the first control signal to the first terminals of the second and fourth capacitors; the sum of the capacitances of the first and second capacitors being approximately equal to the capacitance coupled between the gate and drain of the first MOS transistor; and the sum of the capacitances of the third and fourth capacitors being approximately equal to the capacitance coupled between the gate and source of the first MOS transistor.

Claim 12

A transmission gate comprising: a first MOS transistor of a first conductivity type and having a source, a drain and a gate and having a first parasitic capacitance coupled between the gate and drain, and having a second parasitic capacitance coupled between the gate and source; first, second, third and fourth capacitors each having first and second terminals; the second terminals of the first and second capacitors being coupled together and being coupled to the drain of the first MOS transistor; the second terminals of the third and fourth capacitors being coupled to the source of the first MOS transistor; means for applying a first control signal to the first terminals of the first and third capacitors, a delayed and inverted version of the first control signal to the gate of the first MOS transistor, and a further delayed version of the first control signal to the first terminals of the second and fourth capacitors; the sum of the capacitances of the first and second capacitors being approximately equal to the capacitance coupled between the gate and drain of the first MOS transistor; and the sum of the capacitances of the third and fourth capacitors being approximately equal to the capacitance coupled between the gate and source of the first MOS transistor.

Claim 13

The transmission gate of claim 10 in which each of the capacitors is a separate MOS transistor in which the gate serves as a first terminal of the capacitor and the drain and source are coupled together and serve as a second terminal of the capacitor.

Claim 14

The transmission gate of claim 11 in which the width of the channel of each of the MOS transistors comprising the capacitors is one quarter the width of the channel of the first MOS transistor.

Claim 15

The transmission gate of claim 12 is which each of the transistors is of the n-channel type.

Claim 16

The transmission gate of claim 12 is which each of the transistors is of the p-channel type.

Claim 17

The transmission gate of claim 12 in which the first MOS transistor is an n-channel MOS transistor and the transistors which form the four capacitors are each a p-channel MOS transistor.

Claim 18

The transmission gate of claim 12 in which the first MOS transistor is a p-channel MOS transistor and the transistors which form the four capacitors are each an n-channel MOS transistor.

Claim 19

The transmission gate of claim 10 in which the means for applying the control pulses comprises first and second inverters with an input of the first inverter being coupled to the first terminals of the first and third capacitors, an output of the first inverter being coupled to the gate of the first MOS transistor and to an input of the second inverter, and with an output of the second inverter being coupled to the first terminals of the second and fourth capacitors.

Claim 20

The transmission gate of claim 17 in which each of the first and second inverters introduces the same delay to a control pulse passing therethrough.

Claim 21

The gate of claim 18 in which each of the transistors having the source and drain thereof coupled together to form a capacitor has a channel width equal to one-quarter the channel width of the first transistor and having essentially the same other parameters as the first transistor.

Claim 22

A transmission get comprising: a first MOS transistor of a first conducting type having a source, a drain and a gate, having a first parasitic capacitance coupled between the gate and drain, and having a second parasitic capacitance coupled between the gate and source; first, second, third and fourth capacitors each capacitor being formed of a separate MOS transistor having a source, drain and gate the gate serving as a first terminal of the capacitor and the drain and source being coupled together and serving as a second terminal of the capacitor; the second terminals of the first and second capacitors being coupled together and being coupled to the drain of the first MOS transistor; the second terminals of the third and fourth capacitors being coupled to the source of the first MOS transistor; first and second inverters each having an input terminal and an output terminal; a transmission gate control terminal being coupled to the first terminals of the first and third capacitors and to the input terminal of the first inverter; the output terminal of the first inverter being coupled to the gate of the first MOS transistor and to the input terminal of the second inverter; the output terminal of the second inverter being coupled to the first terminals of the second and fourth capacitors; the sum of the capacitances of the first and second capacitors being approximately equal to the capacitance coupled between the gate and drain of the first MOS transistor; and the sum of the capacitance of the third and fourth capacitors being approximately equal to the capacitance coupled between the gate and source of the first MOS transistor.

Claim 23

A transmission get comprising: a first MOS transistor of a first conducting type having a source, a drain and a gate, having a first parasitic capacitance coupled between the gate and drain, and having a second parasitic capacitance coupled between the gate and source; first, second, third and fourth capacitors each capacitor being formed of a separate MOS transistor having a source, drain and gate the gate serving as a first terminal of the capacitor and the drain and source being coupled together and serving as a second terminal of the capacitor; the second terminals of the first and second capacitors being coupled together and being coupled to the drain of the first MOS transistor; the second terminals of the third and fourth capacitors being coupled to the source of the first MOS transistor; first and second inverters each having an input terminal and an output terminal; a transmission gate control terminal being coupled to the first terminals of the first and third capacitors and to the input terminal of the first inverter; the output terminal of the first inverter being coupled to the gate of the first MOS transistor and to the input terminal of the second inverter; the output terminal of the second inverter being coupled to the first terminals of the second and fourth capacitors; the sum of the capacitances of the first and second capacitors being approximately equal to the capacitance coupled between the gate and drain of the first MOS transistor; and the sum of the capacitance of the third and fourth capacitors being approximately equal to the capacitance coupled between the gate and source of the first MOS transistor.

Claim 24

The transmission gate of claim 20 wherein the first and second capacitors have approximately equal capacitances and the third and fourth capacitors have approximately equal capacitances.

Claim 25

The transmission gate of claim 21 in which the width of each channel of the transistors which are configured to be the four capacitors is one quarter the width of the first transistor.

Claim 26

The transmission gate of claim 22 wherein the first transistor and the transistors which are the four capacitors are all n-channel transistors.

Claim 27

The transmission gate of claim 22 wherein the first MOS transistor and the transistors which are the four capacitors are all p-channel transistors.

Claim 28

The transmission gate of claim 22 wherein the first transistor is of the one conductivity type and the transistors which form the capacitors are of the opposite conductivity type.

Claim 29

The transmission gate of claim 25 wherein the first transistor is an n-channel MOS transistor and the transistors which form the capacitors are all p-channel transistors.

Claim 30

The transmission gate of claim 25 wherein the first transistor is a p-channel MOS transistor and the transistors which form the capacitors are all n-channel transistors.

Claim 31

Circuitry comprising: a first MOS transistor of a first conductivity type and having first and second output terminals and a gate terminal and having a first parasitic capacitance coupled between the gate terminal and the first output terminal and having a second parasitic capacitance coupled between the gate terminal and the second output terminal; second and third MOS transistors of the opposite conductivity type of the first MOS transistor with each having first and second output terminals and a gate terminal and each having a first parasitic capacitance coupled between the gate terminal and the first output terminal thereof and having a second parasitic capacitance coupled between the gate terminal and the second output terminal thereof; the two output terminals of the second transistor being coupled together and being coupled to the first output terminal of the first transistor and to a first input/output terminal of the circuitry; the two output terminals of the third transistor being coupled together and being coupled to the second output terminal of the first transistor and to a second input/output terminal of the circuitry; and a first inverter having an input terminal and an output terminal with the input terminal being coupled to the gate terminal of the first transistor and to a control terminal of the circuitry and with the output terminal being coupled to the gate terminals of the second and third transistors; the capacitance between the gate terminal and the output terminals of the second transistor being approximately equal to the first parasitic capacitance; and the capacitance between the gate terminal and the first and second output terminals of the third MOS transistor being approximately equal to that of the second parasitic capacitance.

Claim 32

Circuitry comprising: a first MOS transistor of a first conductivity type and having first and second output terminals and a gate terminal and having a first parasitic capacitance coupled between the gate terminal and the first output terminal and having a second parasitic capacitance coupled between the gate terminal and the second output terminal; second and third MOS transistors of the opposite conductivity type of the first MOS transistor with each having first and second output terminals and a gate terminal and each having a first parasitic capacitance coupled between the gate terminal and the first output terminal thereof and having a second parasitic capacitance coupled between the gate terminal and the second output terminal thereof; the two output terminals of the second transistor being coupled together and being coupled to the first output terminal of the first transistor and to a first input/output terminal of the circuitry; the two output terminals of the third transistor being coupled together and being coupled to the second output terminal of the first transistor and to a second input/output terminal of the circuitry; and a first inverter having an input terminal and an output terminal with the input terminal being coupled to the gate terminal of the first transistor and to a control terminal of the circuitry and with the output terminal being coupled to the gate terminals of the second and third transistors; the capacitance between the gate terminal and the output terminals of the second transistor being approximately equal to the first parasitic capacitance; and the capacitance between the gate terminal and the first and second output terminals of the third MOS transistor being approximately equal to that of the second parasitic capacitance.

Claim 33

The circuitry of claim 28 wherein the first, second and third transistors are n-channel, p-channel and p-channel MOS transistors, respectively.

Claim 34

The circuitry of claim 28 wherein the first, second and third transistors are p-channel, n-channel and n-channel MOS transistors, respectively.

Claim 35

Circuitry comprising: a first field effect transistor of a first conductivity type and having first and second output terminals and a control terminal and having a first parasitic capacitance coupled between the control terminal and the first output terminal and having a second parasitic capacitance coupled between the control terminal and the second output terminal; first and second capacitance means each having first and second terminals; first and second inverters each having an input terminal and an output terminal; a first circuitry input/output terminal being coupled to the first output terminal of the first transistor; a second circuitry input/output terminal being coupled to the first terminals of the first and second capacitive means and to the second output terminal of the first transistor; the second terminal of the first capacitive means being coupled to the input terminal of the first inverter; the output terminal of the first inverter being coupled to the input terminal of the second inverter and to the control terminal of the first transistor; the output terminal of the second inverter being coupled to the second terminal of the second capacitive means; and the first and second capacitive means have approximately equal capacitances with the sum of the two being approximately equal to the capacitance of the second parasitic capacitance.

Claim 36

Circuitry comprising: a first field effect transistor of a first conductivity type and having first and second output terminals and a control terminal and having a first parasitic capacitance coupled between the control terminal and the first output terminal and having a second parasitic capacitance coupled between the control terminal and the second output terminal; first and second capacitance means each having first and second terminals; first and second inverters each having an input terminal and an output terminal; a first circuitry input/output terminal being coupled to the first output terminal of the first transistor; a second circuitry input/output terminal being coupled to the first terminals of the first and second capacitive means and to the second output terminal of the first transistor; the second terminal of the first capacitive means being coupled to the input terminal of the first inverter; the output terminal of the first inverter being coupled to the input terminal of the second inverter and to the control terminal of the first transistor; the output terminal of the second inverter being coupled to the second terminal of the second capacitive means; and the first and second capacitive means have approximately equal capacitances with the sum of the two being approximately equal to the capacitance of the second parasitic capacitance.

Claim 37

The circuitry of claim 31 wherein each one of the first and second capacitive means is a separate field effect transistor having first and second output terminals and a control terminal; with the first terminal of each capacitive means being the two output terminals of its corresponding transistor and the second terminal of each capacitive means being the control terminal of its corresponding transistor.

Claim 38

The circuitry of claim 32 wherein all the transistors are MOS transistors and each of the transistors which form the first and second capacitive means have the same geometry as the first transistor except that the first transistor has a channel width which is four times as large as each of the other transistors.

Claim 39

The circuitry of claim 33 wherein the first transistor and the transistors which comprise the first and second capacitive means are all n-channel MOS transistors.

Claim 40

The circuitry of claim 33 wherein the first transistor and the transistors which comprise the first and second capacitive means are all p-channel MOS transistors.

Claim 41

The circuitry of claim 33 wherein the first transistor is of first conductivity type and the transistors which comprise the first and second capacitors are of the opposite conductivity type.

Claim 42

Circuitry comprising: a first field effect transistor of a first conductivity type and having first and second output terminals and a gate terminal and having a first parasitic capacitance coupled between the gate terminal and the first output terminal and having a second parasitic capacitance coupled between the gate terminal and the second output terminal; first and second capacitance means each having first and second terminals; first, second, third and fourth inverters each having an input terminal and an output terminal; a first circuitry input/output terminal being coupled to the first terminal of the first capacitive means and to the first output terminal of the first transistor; a second circuitry input/output terminal being coupled to the first terminal of the second capacitive means and to the second output terminal of the first transistor; the second terminals of the first and second capacitive means being coupled to the outputs of the third and fourth inverters; the output terminal of the first inverter being coupled to the input terminal of the second inverter; the output terminal of the second inverter being coupled to the gate terminal of the first transistor and to the input of the third inverter; the first capacitive means having a capacitance approximately equal to the capacitance of the first parasitic capacitance; and the second capacitive means having a capacitance approximately equal to the capacitance of the second parasitic capacitance.

Claim 43

Circuitry comprising: a first field effect transistor of a first conductivity type and having first and second output terminals and a gate terminal and having a first parasitic capacitance coupled between the gate terminal and the first output terminal and having a second parasitic capacitance coupled between the gate terminal and the second output terminal; first and second capacitance means each having first and second terminals; first, second, third and fourth inverters each having an input terminal and an output terminal; a first circuitry input/output terminal being coupled to the first terminal of the first capacitive means and to the first output terminal of the first transistor; a second circuitry input/output terminal being coupled to the first terminal of the second capacitive means and to the second output terminal of the first transistor; the second terminals of the first and second capacitive means being coupled to the outputs of the third and fourth inverters; the output terminal of the first inverter being coupled to the input terminal of the second inverter; the output terminal of the second inverter being coupled to the gate terminal of the first transistor and to the input of the third inverter; the first capacitive means having a capacitance approximately equal to the capacitance of the first parasitic capacitance; and the second capacitive means having a capacitance approximately equal to the capacitance of the second parasitic capacitance.

Claim 44

The circuitry of claim 37 wherein the first and second capacitive means are each a separate field effect transistor having two output terminals and a gate terminal, the first terminal of each capacitive means being the two output terminals of its corresponding transistor, and the second terminal of each capacitive means being the gate terminal of its corresponding transistor.

Claim 45

The circuitry of claim 38 wherein all the transistors are MOS transistors and each of the transistors which form the first and second capacitive means has the same geometry as the first transistor except that the first transistor has a channel width which is two times as large as each of the other transistors.

Claim 46

The circuitry of claim 39 wherein the first transistor and the transistors which comprise the first and second capacitive means are all n-channel MOS transistors.

Claim 47

The circuitry of claim 40 wherein the first transistor and the transistors which comprise the first and second capacitive means are all p-channel MOS transistors.

Claim 48

The circuitry of claim 41 wherein the first transistor is of first conductivity type and the transistors which comprise the first and second capacitive means are of the opposite conductivity type.