Method for making single and double gate field effect transistors with sidewall source-drain contacts

Claim 1

Method for making a field effect transistor (50) on a support structure (51), comprising the steps of: (a) forming a channel layer (55), (b) forming a top gate insulator layer (52) on said channel layer (55), (c)forming a top gate (53) on said top gate insulator layer (52), (d) forming a gate pillar (59) on said top gate (53), (e) forming insulating sidewall layers (58.1, 58.2) adjacent to said top gate (53) and gate pillar (59) (f) forming an integral drain region (50.1) and source region (50.2) within said channel layer (55) by introduction of dopants, (g) forming conductive amorphous silicon sidewalls (57.1, 57.2) on either side of, and adjacent to said insulating sidewall layers (58.1, 58.2), one of said amorphous silicon sidewalls (57.1) being connected to said drain region (50.1) and one (57.2) being connected to said source region (50.2), (h) etching said channel layer (55) using said top gate (53), gate pillar (59), insulating sidewall layers (58.1, 58.2), and amorphous silicon sidewalls (57.1, 57.2) as mask, thereby transferring the lateral extension of said mask into said channel layer (55), providing for a channel (55) with integral drain region (50.1) and source region (50.2) being raised with respect to said support structure (51).