Semiconductor memory device and method for fabricating the same

Claim 1

A semiconductor memory device comprising; a semiconductor substrate of a first conductivity-type having a field region; a field insulating layer formed on the field region so that a plurality of active regions are formed in one direction at predetermined intervals; a plurality of charge input/output stages formed on the semiconductor substrate of the active regions at predetermined intervals; a tunnelling dielectric layer formed on the semiconductor substrate, the tunnelling dielectric layer having a contact hole in the charge input/output stage; a plurality of floating gates formed in a matrix arrangement on the tunnelling dielectric layer above the active regions between the charge input/output stages; a ferroelectric layer formed on the surface of the semiconductor substrate including the floating gates, the ferroelectric layer having a contact hole at the charge input/output stage; a plurality of wordlines each formed on the ferroelectric layer above the floating gates perpendicular to the active regions; an interlevel insulating layer formed on the wordlines, the interlevel insulating layer having a contact hole in the charge input/output stage; and a plurality of bitlines formed on the interlevel insulating layer to electrically connect the charge input/output stages formed on the same active region.