US5315546A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile semiconductor memory using a thin film transistor
Assignee: Toshiba Corp
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Filing: 1991-05-29
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Granted: 1994-05-24
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Expires: 2011-05-29
Abstract
Abstract A MOS transistor has a floating gate, which forms a memory cell of EPROM, and a control gate. The control gate is formed of a thin film. An impurity concentration of a region corresponding to the floating gate is lower than that of the other regions. The region having low impurity concentration functions as a channel region of a thin film transistor. The floating gate functions as a gate of the thin film transistor. In the memory cell in which an electron is written in the floating gate, a threshold voltage of the thin film transistor rises, and the thin film transistor is set to be in an off state. In the memory cell in which no electron is written in the floating gate, the threshold voltage of the thin film transistor lowers, and the thin film transistor is set to be in an on state. If the voltage of said control gate rises in a reading operation, an inversion layer is formed in the only cell of the erasing state and the high voltage of the control gate is supplied to a channel region, and the MOS transistor is turned on. Due to this, the voltage, which is higher than the threshold value of the memory cell of the writing state, can be supplied to the control gate.
Inventors
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10D30/01; H10D30/021; H10D30/0411; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
153 words
A semiconductor memory device, comprising: a semiconductor substrate; a diffusion layer formed in said semiconductor substrate and serving as a source and drain region; a floating gate formed on said semiconductor substrate to be insulated from said semiconductor substrate; a control gate made of a thin film and formed on said floating gate to be insulated from said floating gate; and a transistor including said control gate and said floating gate wherein one end of a current path of said insulating gate transistor is connected to a bit line and the other end is connected to a power source and said control gate is connected to a word line, and a portion of said control gate corresponding to said floating gate is a channel region having an impurity concentration, which is lower than that of other portions of the control gate, and said floating gate is a gate electrode controlling said channel region.
Claim 2
Dependent Claim
153 words
A semiconductor memory device, comprising: a semiconductor substrate; a diffusion layer formed in said semiconductor substrate and serving as a source and drain region; a floating gate formed on said semiconductor substrate to be insulated from said semiconductor substrate; a control gate made of a thin film and formed on said floating gate to be insulated from said floating gate; and a transistor including said control gate and said floating gate wherein one end of a current path of said insulating gate transistor is connected to a bit line and the other end is connected to a power source and said control gate is connected to a word line, and a portion of said control gate corresponding to said floating gate is a channel region having an impurity concentration, which is lower than that of other portions of the control gate, and said floating gate is a gate electrode controlling said channel region.
Claim 3
Dependent Claim
34 words
A device according to claim 1, wherein conductivity of said transistor differs with a writing state that an electron is injected in said floating gate and an erasing state that said electron is discharged.
Claim 4
Dependent Claim
38 words
A device according to claim 2, wherein said drain of said insulating gate transistor is connected to said bit line, said source is connected to a power source, and said control gate is connected to said word line.
Claim 5
Dependent Claim
14 words
A device according to claim 1, wherein said thin film is formed of polysilicon.
Claim 6
Dependent Claim
15 words
A device according to claim 1, wherein said thin film is formed of amorphous silicon.
Claim 7
Dependent Claim
16 words
A device according to claim 1, wherein said thin film is formed of single crystal silicon.
Claim 8
Dependent Claim
221 words
A semiconductor device, comprising: an insulating gate transistor serving as a memory cell having a floating gate and a control gate wherein one end of a current path of said insulating gate transistor is connected to a bit line and another end is connected to a power source, and said control gate is connected to a word line; and a transistor including said control gate and said floating gate wherein said control gate is formed of a thin film, a portion corresponding to said floating gate is a channel region having an impurity concentration, which is lower than that of other portions of said control gate, said floating gate is a gate electrode controlling said channel region, a threshold voltage of said transistor of said memory cell, in which an electron is injected in said floating gate, increases and said transistor is set to be in an off state, said threshold voltage of said transistor of said memory cell, in which the electron is emitted from said floating gate, decreases and said thin film transistor is set to be in an on state, and if the voltage of said control gate increases in a reading operation, the high voltage of said control gate is supplied to a channel region of the on-state transistor, and said insulating gate transistor is turned on.
Claim 9
Dependent Claim
221 words
A semiconductor device, comprising: an insulating gate transistor serving as a memory cell having a floating gate and a control gate wherein one end of a current path of said insulating gate transistor is connected to a bit line and another end is connected to a power source, and said control gate is connected to a word line; and a transistor including said control gate and said floating gate wherein said control gate is formed of a thin film, a portion corresponding to said floating gate is a channel region having an impurity concentration, which is lower than that of other portions of said control gate, said floating gate is a gate electrode controlling said channel region, a threshold voltage of said transistor of said memory cell, in which an electron is injected in said floating gate, increases and said transistor is set to be in an off state, said threshold voltage of said transistor of said memory cell, in which the electron is emitted from said floating gate, decreases and said thin film transistor is set to be in an on state, and if the voltage of said control gate increases in a reading operation, the high voltage of said control gate is supplied to a channel region of the on-state transistor, and said insulating gate transistor is turned on.
Claim 10
Dependent Claim
162 words
A semiconductor memory device comprising: a select transistor having a gate, a source, and a drain, wherein said gate is connected to a select line, and said drain is connected to a column line; a memory transistor of an insulating gate type having a floating gate in which electrons are injected by a tunnel effect and from which electrons are emitted by a tunnel effect, and a control gate, wherein a drain of said memory transistor is connected to the source of said select transistor and a source of said memory transistor is connected to a power source, and said control gate is connected to a program line; and a transistor including said control gate and said floating gate wherein a portion of said control gate corresponding to said floating gate is a channel region having impurity concentration, which is lower than that of other portions of said control gate, and said floating gate is a gate electrode controlling said channel region.
Claim 11
Dependent Claim
162 words
A semiconductor memory device comprising: a select transistor having a gate, a source, and a drain, wherein said gate is connected to a select line, and said drain is connected to a column line; a memory transistor of an insulating gate type having a floating gate in which electrons are injected by a tunnel effect and from which electrons are emitted by a tunnel effect, and a control gate, wherein a drain of said memory transistor is connected to the source of said select transistor and a source of said memory transistor is connected to a power source, and said control gate is connected to a program line; and a transistor including said control gate and said floating gate wherein a portion of said control gate corresponding to said floating gate is a channel region having impurity concentration, which is lower than that of other portions of said control gate, and said floating gate is a gate electrode controlling said channel region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |