Nonvolatile semiconductor memory

Claim 2

A nonvolatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type; source and drain diffusion layers in said substrate; a channel region between said source and drain diffusion layers; a first insulation film continuously on said channel region and said drain diffusion layer adjacent to said channel region and having a first thickness; a floating gate layer on said first insulation film; a second insulation film on said floating gate layer, a thin film portion of said second insulation film having a thickness less than the first thickness and a remaining portion of said second insulation film having a thickness substantially equal to the first thickness; and a control gate layer on said second insulation film.

Claim 3

A nonvolatile semiconductor memory according to claim 1, wherein the film thickness of said thin film portion of said second insulation film is such that a tunnel current may flow in said thin film portion when an electric field of a predetermined intensity is applied between said control gate layer and said drain diffusion layer.

Claim 4

A nonvolatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type; a first, second and third diffusion layers of a second conductivity type in said substrate; a first channel region between said first and second diffusion layers; a second channel region between said second and third diffusion layers; a first insulation film continuously on said first channel region and said second diffusion layer adjacent to said first channel region and having a first thickness; a floating gate layer on said first insulation film; a second insulation film on said floating gate layer, a thin film portion of said second insulation film having a thickness less than the first thickness and a remaining portion of said second insulation film having a thickness substantially equal to the first thickness; a control gate layer on said second insulation film; a third insulation film on said second channel region and having a film thickness substantially equal to the first thickness; a selection gate layer on said third insulation film; a control gate line for applying preset voltages to said control gate layer int he data programming, erasing and readout modes; a selection gate line for applying preset voltages to said selection gate layer in the data programming, erasing and readout modes; a source line for applying a preset voltage to said first diffusion layer; and a bit line for applying preset voltages to said third diffusion layer in the data programming, erasing and readout modes.

Claim 5

A nonvolatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type; a first, second and third diffusion layers of a second conductivity type in said substrate; a first channel region between said first and second diffusion layers; a second channel region between said second and third diffusion layers; a first insulation film continuously on said first channel region and said second diffusion layer adjacent to said first channel region and having a first thickness; a floating gate layer on said first insulation film; a second insulation film on said floating gate layer, a thin film portion of said second insulation film having a thickness less than the first thickness and a remaining portion of said second insulation film having a thickness substantially equal to the first thickness; a control gate layer on said second insulation film; a third insulation film on said second channel region and having a film thickness substantially equal to the first thickness; a selection gate layer on said third insulation film; a control gate line for applying preset voltages to said control gate layer int he data programming, erasing and readout modes; a selection gate line for applying preset voltages to said selection gate layer in the data programming, erasing and readout modes; a source line for applying a preset voltage to said first diffusion layer; and a bit line for applying preset voltages to said third diffusion layer in the data programming, erasing and readout modes.

Claim 6

A nonvolatile semiconductor memory according to claim 3, wherein the film thickness of said thin film portion of said second insulation film is such that a tunnel current may flow in said thin film portion when an electric field of a predetermined intensity is applied between said control gate layer and said drain diffusion layer.

Claim 7

A nonvolatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type; a first, second and third diffusion layers of a second conductivity type in said substrate; a first channel region between said first and second diffusion layers; a second channel region between said second and third diffusion layers; a first insulation film continuously on said first channel region and said second diffusion layer adjacent to said first channel region and having a first thickness; a floating gate layer on said first insulation film; a second insulation film on said floating gate layer, a thin film portion of said second insulation film having a thickness less than the first thickness and a remaining portion of said second insulation film having a thickness substantially equal to the first thickness; a control gate layer on said second insulation film; a third insulation film on said second channel region and having a film thickness substantially equal to the first thickness; a selection gate layer on said third insulation film; a control gate line for applying preset voltages to said control gate layer in the data programming, erasing and readout modes; a selection gate line for applying preset voltages to said selection gate layer in the data programming, erasing and readout modes; a source line for applying a preset voltage to said first diffusion layer; and a bit line for applying preset voltages to said third diffusion layer in the data programming, erasing and readout modes; a power source node supplied with a power source potential; a load circuit connected between said bit line and power source node; and a sense circuit connected to said bit line, for detecting the potential of said bit line.

Claim 8

A nonvolatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type; a first, second and third diffusion layers of a second conductivity type in said substrate; a first channel region between said first and second diffusion layers; a second channel region between said second and third diffusion layers; a first insulation film continuously on said first channel region and said second diffusion layer adjacent to said first channel region and having a first thickness; a floating gate layer on said first insulation film; a second insulation film on said floating gate layer, a thin film portion of said second insulation film having a thickness less than the first thickness and a remaining portion of said second insulation film having a thickness substantially equal to the first thickness; a control gate layer on said second insulation film; a third insulation film on said second channel region and having a film thickness substantially equal to the first thickness; a selection gate layer on said third insulation film; a control gate line for applying preset voltages to said control gate layer in the data programming, erasing and readout modes; a selection gate line for applying preset voltages to said selection gate layer in the data programming, erasing and readout modes; a source line for applying a preset voltage to said first diffusion layer; and a bit line for applying preset voltages to said third diffusion layer in the data programming, erasing and readout modes; a power source node supplied with a power source potential; a load circuit connected between said bit line and power source node; and a sense circuit connected to said bit line, for detecting the potential of said bit line.

Claim 9

A nonvolatile semiconductor memory according to claim 5, wherein the film thickness of said thin film portion of said second insulation film is such that a tunnel current may flow in said thin film portion when an electric field of a predetermined intensity is applied between said control gate layer and said drain diffusion layer.

Claim 10

A nonvolatile semiconductor memory according to claim 6, wherein said load circuit is a resistor.

Claim 11

A nonvolatile semiconductor memory according to claim 6, wherein said load circuit is constituted by a MOS transistor which is normally set conductive.

Claim 12

A nonvolatile semiconductor memory according to claim 6, wherein said load circuit is constituted by a MOS transistor which is controlled to be temporarily rendered conductive in response to a clock pulse.

Claim 13

A nonvolatile semiconductor memory according to claim 6, further comprising a combination circuit which is controlled by the clock pulse signal and is supplied with an address signal and which supplies an output signal to said selection gate line.

Claim 14

A nonvolatile semiconductor memory according to claim 4, wherein said sense circuit is an inverter circuit.