US4725980A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read only memory circuit
Assignee: Fujitsu Ltd
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Filing: 1985-11-18
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Granted: 1988-02-16
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Expires: 2005-11-18
Abstract
Abstract A ROM circuit is used in place of a conventional fuse type ROM which is incorporated in a semiconductor integrated circuit network together with other circuit blocks on a chip. The ROM circuit comprises a first transistor having a control and a floating gate and a depletion type second transistor having a gate formed as an extension of the floating gate. The second transistor outputs a high level control signal if hot electrons have been accumulated on the floating gate of the first transistor by the application of a predetermined high level input signal to the control gate thereof, and outputs a low level signal when the high level input signal has not been provided to the control gate. The first transistor is freed from a soft write problem because it is separated from a voltage source in the read mode.
Inventors
- 👤 Hideyuki Wakimoto
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:48
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
207 words
A read only memory (ROM) circuit operatively connected to first and second voltage sources, comprising: terminal means for receiving a predetermined input signal only during a write mode; a first transistor, said first transistor having a channel region, a control gate facing said channel region, a floating gate formed between said channel region and said control gate, a source connected to said first voltage source and a drain, wherein said control gate is connected to said terminal means; second transistor of a depletion type, said second transistor having a gate connected to said floating gate of said first transistor, a source connected to said first voltage source and a drain forming an output node connected to said second voltage source; and first and second resistive means, said first resistive means being connected between said control gate and said drain of said first transistor, and said second resistive means connected between said output node of said second transistor and said second voltage source, wherein said first transistor stores information in accordance with the application of said predetermined input signal to said terminal means, and said second transistor operatively outputs a high or low signal from said output node in accordance with said information stored in said first transistor.
Claim 2
Dependent Claim
207 words
A read only memory (ROM) circuit operatively connected to first and second voltage sources, comprising: terminal means for receiving a predetermined input signal only during a write mode; a first transistor, said first transistor having a channel region, a control gate facing said channel region, a floating gate formed between said channel region and said control gate, a source connected to said first voltage source and a drain, wherein said control gate is connected to said terminal means; second transistor of a depletion type, said second transistor having a gate connected to said floating gate of said first transistor, a source connected to said first voltage source and a drain forming an output node connected to said second voltage source; and first and second resistive means, said first resistive means being connected between said control gate and said drain of said first transistor, and said second resistive means connected between said output node of said second transistor and said second voltage source, wherein said first transistor stores information in accordance with the application of said predetermined input signal to said terminal means, and said second transistor operatively outputs a high or low signal from said output node in accordance with said information stored in said first transistor.
Claim 3
Dependent Claim
51 words
A read only memory (ROM) circuit as set forth in claim 1, having a diffusion layer wherein said first or second resistive means is formed from a part of said diffusion layer and wherein said source or drain region of said first or second transistor is formed in said diffusion layer.
Claim 4
Dependent Claim
25 words
A read only memory (ROM) circuit as set forth in claim 1, wherein each of said first and second transistors has an n-type conduction channel.
Claim 5
Dependent Claim
24 words
A read only memory (ROM) circuit as set forth in claim 1, wherein said first and second transistors are formed on a semiconductor substrate.
Claim 6
Dependent Claim
34 words
A read only memory (ROM) circuit as set forth in claim 4, wherein said floating gate of said first transistor and said gate of said second transistor are formed from the same conductive layer.
Claim 7
Dependent Claim
34 words
A read only memory (ROM) circuit as set forth in claim 5, wherein said floating gate of said first transistor and said gate of said second transistor are embedded in an insulating material matrix.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |