Method of fabricating a field effect transistor with short gate length

Claim 1

A method for fabricating a field effect transistor of a first conductivity type, said method comprising the steps of: forming a gate electrode of a polycrystalline semiconductor on an insulating film provided on a semiconductor substrate; depositing isotropically a spacer material on and around said gate electrode; forming a dummy spacer sidewall by anisotropically etching back said spacer material; forming source/drain diffusion layers using said gate electrode and said dummy spacer sidewall as masks, said source/drain diffusion layers not extending beneath said gate electrode; removing said dummy spacer sidewall after the formation of said source/drain diffusion layers; depositing isotropically a material selected from the group consisting of metal, metal silicide and polycrystalline silicon; and forming a sidewall by anisotropically etching back said deposited material, said sidewall being formed at regions corresponding to said removed dummy spacer sidewall and being thinner than said dummy spacer sidewall and in contact with said gate electrode.

Claim 2

A method for fabricating a field effect transistor of a first conductivity type, said method comprising the steps of: forming a gate electrode of a polycrystalline semiconductor on an insulating film provided on a semiconductor substrate; depositing isotropically a spacer material on and around said gate electrode; forming a dummy spacer sidewall by anisotropically etching back said spacer material; forming source/drain diffusion layers using said gate electrode and said dummy spacer sidewall as masks, said source/drain diffusion layers not extending beneath said gate electrode; removing said dummy spacer sidewall after the formation of said source/drain diffusion layers; depositing isotropically a material selected from the group consisting of metal, metal silicide and polycrystalline silicon; and forming a sidewall by anisotropically etching back said deposited material, said sidewall being formed at regions corresponding to said removed dummy spacer sidewall and being thinner than said dummy spacer sidewall and in contact with said gate electrode.

Claim 6

A method of fabricating a field effect transistor, comprising the steps of: forming a semiconductor gate electrode on an insulating film on a semiconductor substrate; forming a dummy spacer on sides of the gate electrode, the dummy spacer having a first width; implanting impurities into the substrate using the gate electrode and the dummy spacer as a mask; removing the dummy spacer; diffusing the impurities into the substrate to form source/drain layers; and forming a sidewall on sides of the gate electrode at regions corresponding to the removed dummy spacer, the sidewall having a second width that is less than the first width and comprising a material selected from the group consisting of metal, metal silicide and polycrystalline silicon.

Claim 7

A method of fabricating a field effect transistor, comprising the steps of: forming a semiconductor gate electrode on an insulating film on a semiconductor substrate; forming a dummy spacer on sides of the gate electrode, the dummy spacer having a first width; implanting impurities into the substrate using the gate electrode and the dummy spacer as a mask; removing the dummy spacer; diffusing the impurities into the substrate to form source/drain layers; and forming a sidewall on sides of the gate electrode at regions corresponding to the removed dummy spacer, the sidewall having a second width that is less than the first width and comprising a material selected from the group consisting of metal, metal silicide and polycrystalline silicon.

Claim 11

A method of fabricating a field effect transistor, comprising the steps of: forming a semiconductor gate electrode on an insulating film on a semiconductor substrate; forming a dummy spacer on sides of the gate electrode, the dummy spacer having a first width; implanting impurities into the substrate using the gate electrode and the dummy spacer as a mask, the first width being sufficient to prevent the impurities from extending beneath the gate electrode when the impurities are diffused into the substrate; removing the dummy spacer; diffusing the impurities into the substrate to form source/drain layers which do not extend beneath the gate electrode; and forming a sidewall on sides of the gate electrode at regions corresponding to the removed dummy spacer, the sidewall comprising a material selected from the group consisting of metal, metal silicide and polycrystalline silicon, wherein the sidewall has a second width that is less than the first width.

Claim 12

A method of fabricating a field effect transistor, comprising the steps of: forming a semiconductor gate electrode on an insulating film on a semiconductor substrate; forming a dummy spacer on sides of the gate electrode, the dummy spacer having a first width; implanting impurities into the substrate using the gate electrode and the dummy spacer as a mask, the first width being sufficient to prevent the impurities from extending beneath the gate electrode when the impurities are diffused into the substrate; removing the dummy spacer; diffusing the impurities into the substrate to form source/drain layers which do not extend beneath the gate electrode; and forming a sidewall on sides of the gate electrode at regions corresponding to the removed dummy spacer, the sidewall comprising a material selected from the group consisting of metal, metal silicide and polycrystalline silicon, wherein the sidewall has a second width that is less than the first width.