SOI CMOS structure

Claim 1

An integrate circuit comprising: a substrate of dielectric material, a continuous sheet of single crystal semiconductor material on said substrate of dielectric material, said continuous sheet of single crystal semiconductor material having a continuous recessed region having a first thickness, said recessed region being patterned to leave a plurality of mesas surrounded by said recessed region, said mesas having a second thickness greater than said first thickness, a plurality of said mesas each having at least one field effect transistor formed thereon, each said field effect transistor having a source, drain, a channel therebetween, and a gate, wherein said second thickness is selected to permit said drain and source to form a substantially fully depleted depletion region extending to said substrate below each of said drain and source, respectively, while leaving therebetween and under said channel a neutral, partially depleted region of said recessed region for interconnection with adjoining regions of said recessed region of said continuous sheet, said continuous sheet of single crystal semiconductor material serving as two-dimensional ohmic interconnection between at least two of said field effect transistors, said field effect transistors being of the same channel type, and said continuous sheet of single semiconductor material having a common substrate contact for interconnecting a plurality of said field effect transistors thereto.