Multiprocessor system capable of isolating failure processor based on initial diagnosis result

Claim 2

A multiprocessor system comprising a plurality of processor boards, each of which includes a plurality of processors, wherein: each of said processor boards has a nonvolatile memory for storing therein an initial diagnosis result of each of said processors on the processor board, a master processor in each of said processor boards is selected based on the initial diagnosis result stored in said nonvolatile memory at system boot-up, and an overall master processor of said multiprocessor system is selected from master processors, said system further comprising means for issuing an interruption to one of all of the processors in the boards and all of the processors in the system for acknowledging a normal condition of the initial diagnosis result, wherein, with said nonvolatile memory each processor executes initial diagnosis simultaneously.

Claim 3

The multiprocessor system according to claim 1, wherein the master processors are simultaneously determined.

Claim 4

The multiprocessor system according to claim 1, wherein only one said master processor is determined in each processor board, and only one said overall master processor is determined in the system.

Claim 5

A multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors, wherein: each of said processor boards includes: a processor controller, provided with each of said processors, for controlling the connection of said processors to said system bus; and a nonvolatile memory, commonly used in said processor controller, for storing a result of an initial diagnosis of each of said processors on said processor board; each of said processors includes: means for selecting a master processor in said processor boards based on the initial diagnosis result stored in said nonvolatile memory; and means for selecting an overall master processor for the multiprocessor system from master processors selected in said processor boards.

Claim 6

A multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors, wherein: each of said processor boards includes: a processor controller, provided with each of said processors, for controlling the connection of said processors to said system bus; and a nonvolatile memory, commonly used in said processor controller, for storing a result of an initial diagnosis of each of said processors on said processor board; each of said processors includes: means for selecting a master processor in said processor boards based on the initial diagnosis result stored in said nonvolatile memory; and means for selecting an overall master processor for the multiprocessor system from master processors selected in said processor boards.

Claim 7

The multiprocessor system as claimed in claim 4, wherein said means for selecting the master processor in each of said processor boards selects as the master processor such a processor having a minimum CPU number from the processors in which the initial diagnosis is ended under normal condition within the processor board.

Claim 8

The multiprocessor system as claimed in claim 5, wherein said means for selecting the overall master processor of the multiprocessor system selects the processor having the minimum CPU number on the processor board as the overall master processor of this system.

Claim 9

The multiprocessor system as claimed in claim 6, wherein said nonvolatile memory is connected via a local bus to said processor controller.

Claim 10

The multiprocessor system as claimed in claim 6, further includes: a storage connected to said system bus for storing therein the initial diagnosis result stored in said nonvolatile memory of said processor board.

Claim 11

The multiprocessor system as claimed in claim 6, wherein said processor controller isolates the corresponding processor from said system bus when the initial diagnosis of said corresponding processor is not ended under normal condition.

Claim 12

The multiprocessor system as claimed in claim 6, wherein said processor further includes means for issuing an interruption to all of the processors provided within said processor board when said processor is selected as the master processor of said processor board.

Claim 13

The multiprocessor system as claimed in claim 6, wherein said processor further includes means for issuing an interruption to all of the processors provided within said multiprocessor system when said processor is selected as the master processor of said multiprocessor system.

Claim 14

The multiprocessor system according to claim 4, wherein the master processors are simultaneously determined.

Claim 15

The multiprocessor system according to claim 1, further comprising means for issuing an interruption to one of all of the processors in the boards and all of the processors in the system for acknowledging a normal condition of the initial diagnosis result, wherein, with said nonvolatile memory, each processor executes initial diagnosis simultaneously, wherein only one said master processor is determined in each processor board, and only one said overall master processor is determined in the system initial diagnosis.

Claim 16

A multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors, wherein: each of said processor boards includes: a processor controller, provided with each of said processors, for controlling the connection of said processors to said system bus; and a nonvolatile memory, commonly used in said processor controller, for storing a result of an initial diagnosis of each of said processors on said processor board; each of said processors includes: means for selecting a master processor in said processor boards based on the initial diagnosis result stored in said nonvolatile memory; and means for selecting an overall master processor for the multiprocessor system from master processors selected in said processor boards, wherein said means for selecting the master processor in each of said processor boards selects as the master processor such a processor having a minimum CPU number from the processors in which the initial diagnosis is ended under normal condition within the processor board, wherein said means for selecting the overall master processor of the multiprocessor system selects the processor having the minimum CPU number on the processor board as the overall master processor of this system, said multiprocessor system further including: a storage connected to said system bus for storing therein the initial diagnosis result stored in said nonvolatile memory of said processor board, wherein said processor selected as the overall master processor of the multiprocessor system indicates a processor controller corresponding to the processor where the initial diagnosis is not ended under normal condition so as to isolate said processor from said system bus based upon the initial diagnosis result stored in said storage.

Claim 17

A multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors, wherein: each of said processor boards includes: a processor controller, provided with each of said processors, for controlling the connection of said processors to said system bus; and a nonvolatile memory, commonly used in said processor controller, for storing a result of an initial diagnosis of each of said processors on said processor board; each of said processors includes: means for selecting a master processor in said processor boards based on the initial diagnosis result stored in said nonvolatile memory; and means for selecting an overall master processor for the multiprocessor system from master processors selected in said processor boards, wherein said means for selecting the master processor in each of said processor boards selects as the master processor such a processor having a minimum CPU number from the processors in which the initial diagnosis is ended under normal condition within the processor board, wherein said means for selecting the overall master processor of the multiprocessor system selects the processor having the minimum CPU number on the processor board as the overall master processor of this system, said multiprocessor system further including: a storage connected to said system bus for storing therein the initial diagnosis result stored in said nonvolatile memory of said processor board, wherein said processor selected as the overall master processor of the multiprocessor system indicates a processor controller corresponding to the processor where the initial diagnosis is not ended under normal condition so as to isolate said processor from said system bus based upon the initial diagnosis result stored in said storage.

Claim 18

A multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors, wherein: each of said processor boards includes: a processor controller, provided with each of said processors, for controlling the connection of said processors to said system bus; and a nonvolatile memory, commonly used in said processor controller, for storing a result of an initial diagnosis of each of said processors on said processor board; each of said processors includes: means for selecting a master processor in said processor boards based on the initial diagnosis result stored in said nonvolatile memory; and means for selecting an overall master processor for the multiprocessor system from master processors selected in said processor boards, wherein said means for selecting the master processor in each of said processor boards selects as the master processor such a processor having a minimum CPU number from the processors in which the initial diagnosis is ended under normal condition within the processor board, wherein said means for selecting the overall master processor of the multiprocessor system selects the processor having the minimum CPU number on the processor board as the overall master processor of this system, wherein said processor further includes means for issuing an interruption to all of the processors provided within said multiprocessor system when said processor is selected as the master processor of said multiprocessor system, wherein both of said system bus and the local bus of each processor board are driven at different voltage levels from each other.

Claim 19

A multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors, wherein: each of said processor boards includes: a processor controller, provided with each of said processors, for controlling the connection of said processors to said system bus; and a nonvolatile memory, commonly used in said processor controller, for storing a result of an initial diagnosis of each of said processors on said processor board; each of said processors includes: means for selecting a master processor in said processor boards based on the initial diagnosis result stored in said nonvolatile memory; and means for selecting an overall master processor for the multiprocessor system from master processors selected in said processor boards, wherein said means for selecting the master processor in each of said processor boards selects as the master processor such a processor having a minimum CPU number from the processors in which the initial diagnosis is ended under normal condition within the processor board, wherein said means for selecting the overall master processor of the multiprocessor system selects the processor having the minimum CPU number on the processor board as the overall master processor of this system, wherein said processor further includes means for issuing an interruption to all of the processors provided within said multiprocessor system when said processor is selected as the master processor of said multiprocessor system, wherein both of said system bus and the local bus of each processor board are driven at different voltage levels from each other.

Claim 20

In a multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors and a nonvolatile memory for storing therein an initial diagnosis result of each of said processors on the processor board, a master processor selecting method comprising: a first step for selecting a plurality of master processors, one for each of said processor boards; and a second step for selecting an overall master processor of the multiprocessor system from the master processors selected in said first step, further comprising a step of issuing an interruption to one of all of the processors in the boards and all of the processors in the system for acknowledging a normal condition of the initial diagnosis result, wherein, with said nonvolatile memory, each processor executes initial diagnosis simultaneously.

Claim 21

In a multiprocessor system for connecting a plurality of processor boards with each other via a system bus, each of said processor boards including a plurality of processors and a nonvolatile memory for storing therein an initial diagnosis result of each of said processors on the processor board, a master processor selecting method comprising: a first step for selecting a plurality of master processors, one for each of said processor boards; and a second step for selecting an overall master processor of the multiprocessor system from the master processors selected in said first step, further comprising a step of issuing an interruption to one of all of the processors in the boards and all of the processors in the system for acknowledging a normal condition of the initial diagnosis result, wherein, with said nonvolatile memory, each processor executes initial diagnosis simultaneously.

Claim 22

The master processor selecting method in the multiprocessor system as claimed in claim 16, wherein said first step selects as a master processor, a processor having a minimum CPU number from the processors in which the initial diagnosis is ended under normal condition in each of said processor boards, and said second step selects the processor having the minimum CPU number on the processor board as the overall master processor of the multiprocessor system.

Claim 23

The master processor selecting method in the multiprocessor system as claimed in claim 17, wherein at said first step, when the processor having a minimum CPU number is selected as the master processor of said processor board, the processor issues an interruption to all of said processors within said processor board, and at said second step, when said processor is selected as the overall master processor of the multiprocessor system, the processor issues an interruption to all of the processors within the multiprocessor system.