US5408647A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic logical CPU assignment of physical CPUs
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-10-02
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Granted: 1995-04-18
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Expires: 2012-10-02
Abstract
Abstract A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.
Inventors
- 👤 John A. Landry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:46
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1417; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F15/00; G06F15/16; G06F15/177; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4405; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
141 words
A method for providing a logical first processor in a multiprocessor computer system, comprising the steps of: assigning initial logical processor values to each processor upon reset of the computer system; starting a timer set for a predetermined timeout upon reset of the computer system; causing all but the first logical processor to halt operations upon reset of the computer system; providing a reset sequence for the first logical processor, which sequence includes performing an operation to a predetermined location; halting said timer upon an operation to said predetermined location; and upon timeout of said timer performing the steps of: indicating said present first logical processor as inoperable; restarting said timer with said predetermined timeout; and decrementing said logical processor values of each processor, whereby the new first logical processor is removed from said halt condition and executes said reset sequence.
Claim 2
Independent Claim
141 words
A method for providing a logical first processor in a multiprocessor computer system, comprising the steps of: assigning initial logical processor values to each processor upon reset of the computer system; starting a timer set for a predetermined timeout upon reset of the computer system; causing all but the first logical processor to halt operations upon reset of the computer system; providing a reset sequence for the first logical processor, which sequence includes performing an operation to a predetermined location; halting said timer upon an operation to said predetermined location; and upon timeout of said timer performing the steps of: indicating said present first logical processor as inoperable; restarting said timer with said predetermined timeout; and decrementing said logical processor values of each processor, whereby the new first logical processor is removed from said halt condition and executes said reset sequence.
Claim 3
Dependent Claim
31 words
The method of claim 1, wherein said reset sequence for said first logical processor includes removing all operable processors from said halt condition after performing said operation to said predetermined location.
Claim 4
Dependent Claim
25 words
The method of claim 1, wherein said initial logical processor value step assigns each processor its physical processor location as its initial logical processor value.
Claim 5
Dependent Claim
169 words
A multiprocessor computer system, comprising: means for resetting the computer system; a plurality of processors, each processor including: means for assigning each processor an initial logical processor value upon reset of the computer system; means for halting each processor if said logical processor value is not a predetermined value upon reset of the computer system; and means for decrementing said logical processor value of each processor upon receipt of a signal and releasing the processor having a logical processor value of said predetermined value from said halt condition; a timer having a predetermined timeout; means for starting said timer upon reset of the computer system; means for causing said processor having said predetermined value to access a predetermined location after reset; means coupled to said timer for halting said timer if said processor having said predetermined value accesses said predetermined location; and means coupled to said timer for providing a signal to each of said processor means for decrementing said logical processor value upon time out of said timer.
Claim 6
Dependent Claim
169 words
A multiprocessor computer system, comprising: means for resetting the computer system; a plurality of processors, each processor including: means for assigning each processor an initial logical processor value upon reset of the computer system; means for halting each processor if said logical processor value is not a predetermined value upon reset of the computer system; and means for decrementing said logical processor value of each processor upon receipt of a signal and releasing the processor having a logical processor value of said predetermined value from said halt condition; a timer having a predetermined timeout; means for starting said timer upon reset of the computer system; means for causing said processor having said predetermined value to access a predetermined location after reset; means coupled to said timer for halting said timer if said processor having said predetermined value accesses said predetermined location; and means coupled to said timer for providing a signal to each of said processor means for decrementing said logical processor value upon time out of said timer.
Claim 7
Dependent Claim
26 words
The multiprocessor system of claim 4, further comprising: means for causing said processor having said predetermined value to remove each operable processors from said halt condition.
Claim 8
Dependent Claim
33 words
The multiprocessor system of claim 4, wherein each processor has a physical location and wherein said means for assigning initial logical processor values assigns the physical location value as the logical processor value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |