High-availability computer system with a support logic for a warm start

Claim 1

A high availability computer system comprising: a plurality of general data processor modules connected respectively as Master/Checker pairs having two logical processors to a general data processor unit, said logical processors are connected to one another within the general data processor unit by a local bus and a bus extension unit; the bus extension unit is connected further to a system bus thereby providing data communication to all of the computer system; a parameter controller communicating through at least one COM-line and at least one respective COM-pin of each bus extension unit to control identification and parameterization during a physical system initialization; each bus extension unit includes an INIT counter maintained by said parameter controller during each initialization; each of said general data processors thus connected to its bus extension unit reads its respective INIT counter and decides whether to continue data processing or to stop; each general data processor receives either a Master or a Checker identification during initialization and stores said identification; identification and parameterization are always assigned the same way such that a logic 0 or a logic 1 of the general data processors always starts the same process; and each INIT counter is incremented after each warm start such that on each subsequent warm start the general data processor performing the initialization is different from the previous general data processor performing the initialization.