Method and apparatus for initializing a multiprocessor system while resetting defective CPU's detected during operation thereof

Claim 1

A multiprocessor system able to set up itself while cutting out defective CPUs from a common bus thereof, said system comprising: a plurality of CPUs connected to the common bus; a single ROM, provided to said common bus, for storing initialization program for setting-up the system when the power of the system is turned on; a single nonvolatile RAM, provided to said common bus, for storing system configuration information indicating mounting status of the plurality of CPUs; an identifier setting register, connected to said common bus, capable of assigning to and reading from an arbitrary CPU a CPU number, for designating assigned CPU numbers to the respective CPUs; a reset controller, having start request information inputs corresponding to each CPU and having report information inputs corresponding to each CPU, and connected to each CPU through corresponding individual hardware reset lines, for controlling said CPUs individually into a reset state by separately enabling each said individual hardware reset line and into a setting-up state by separately disabling each said individual hardware reset line based on said start request information of each CPU, said reset controller having a time-out detection mechanism for monitoring completion of initialization of each CPU, stopping the operation of said time-out detection mechanism based on said report information indicating the completion of initialization of each CPU, and cutting off from the system, at a time of the time-out detection conducted by said time-out detection mechanism, the corresponding CPUs whose records indicates a fault occurrence, thereby initializing the multiprocessor system; a reset status input port provided to the common bus and connected to read the status of each CPU individual hardware reset line, the reset status input port enabling an arbitrary CPU to read the read status through said common bus; and a reset information register, provided to the common bus, for holding said start request information of the selected CPUs and said report information of the completion of initialization of those CPUs given from an arbitrary CPU through said common bus, the reset information register further connected to said start request information inputs and said report information inputs of said reset controller, the reset information register enabling an arbitrary CPU to read said start request information and said report information through said common bus.

Claim 16

A method of resetting a multiprocessor system including a plurality of CPUs, comprising the steps of: designating in a register each of the plurality of CPUs; selecting from among the CPUs designated, a master CPU; starting the master CPU selected; operating the master CPU to select from among the plurality of CPUs, a slave CPU; starting the slave CPU selected; during any previously recited step, determining one CPU of the plurality of CPUs to have a fault; recording the CPU fault including an identification of the one CPU in a register; inhibiting only the one CPU by asserting a reset line coupled to only the one of the plurality of CPUs; and operating the master CPU to load an initial program.

Claim 17

A method of resetting a multiprocessor system including a plurality of CPUs, comprising the steps of: designating in a register each of the plurality of CPUs; selecting from among the CPUs designated, a master CPU; starting the master CPU selected; operating the master CPU to select from among the plurality of CPUs, a slave CPU; starting the slave CPU selected; during any previously recited step, determining one CPU of the plurality of CPUs to have a fault; recording the CPU fault including an identification of the one CPU in a register; inhibiting only the one CPU by asserting a reset line coupled to only the one of the plurality of CPUs; and operating the master CPU to load an initial program.