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US5763312A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating LDD spacers in MOS devices with double spacers and device manufactured thereby

Assignee: Vanguard International Semiconductor Corp
•
Filing: 1997-05-05
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Granted: 1998-06-09
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Expires: 2017-05-05
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Abstract

Abstract In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor stacks. Then form first dielectric spacers of a first dielectric material on the sidewalls of the gate conductor stacks; and form second dielectric spacers of a second dielectric material on the sidewalls of the first dielectric spacers adjacent to the gate conductor stacks thereby forming double sidewall spacers. Form fully doped regions ion implanted into the surface of the substrate self-aligned with the double sidewall spacers. The fully doped regions are self-aligned with the first and second dielectric spacers formed on the gate conductor stacks. The device is covered with a blanket dielectric layer formed by LPCVD from a TEOS source. Above the new dielectric layer, a mask is formed with a contact opening therethrough over a contact region. Then etch away the second dielectric spacers below the contact opening to form self-aligned contact regions reaching down to the substrate between the first dielectric spacers.

Inventors

  • 👤 Erik S. Jeng
  • 👤 Ing-Ruey Liaw

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 22:18
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/021; Y; Y10; Y10S; Y10S257/00; Y10S257/90

Claims Analysis

Total Claims: 24
Claim 1
Independent Claim 163 words
A method of forming a semiconductor device on a doped silicon semiconductor substrate with a pair of gate conductor stacks formed thereon, said gate conductor stacks comprising a gate oxide layer, a gate electrode layer and a dielectric cap layer, comprising the steps as follows: ion implanting lightly doped regions in the surface of said substrate, said lightly doped regions being self-aligned with said gate conductor stacks, forming first dielectric spacers of a first dielectric material on the sidewalls of said gate conductor stacks, forming second dielectric spacers of a second dielectric material on the sidewalls of said first dielectric spacers adjacent to said gate conductor stacks, ion implanting fully doped regions in the surface of said substrate, said fully doped regions being self-aligned with said first and second dielectric spacers formed on said gate conductor stacks, forming a mask with a contact opening therethrough over a contact region, etching away said second dielectric spacers below said contact opening, down to said substrate.
Claim 2
Independent Claim 163 words
A method of forming a semiconductor device on a doped silicon semiconductor substrate with a pair of gate conductor stacks formed thereon, said gate conductor stacks comprising a gate oxide layer, a gate electrode layer and a dielectric cap layer, comprising the steps as follows: ion implanting lightly doped regions in the surface of said substrate, said lightly doped regions being self-aligned with said gate conductor stacks, forming first dielectric spacers of a first dielectric material on the sidewalls of said gate conductor stacks, forming second dielectric spacers of a second dielectric material on the sidewalls of said first dielectric spacers adjacent to said gate conductor stacks, ion implanting fully doped regions in the surface of said substrate, said fully doped regions being self-aligned with said first and second dielectric spacers formed on said gate conductor stacks, forming a mask with a contact opening therethrough over a contact region, etching away said second dielectric spacers below said contact opening, down to said substrate.
Claim 3
Dependent Claim 23 words
A method in accordance with claim 1 wherein said first dielectric spacers have a thickness from about 300 Å to about 700 Å.
Claim 4
Dependent Claim 23 words
A method in accordance with claim 1 wherein said second dielectric spacers have a thickness from about 200 Å to about 800 Å.
Claim 5
Dependent Claim 23 words
A method in accordance with claim 2 wherein said second dielectric spacers have a thickness from about 200 Å to about 800 Å.
Claim 6
Dependent Claim 17 words
A method in accordance with claim 1 wherein said first dielectric spacers are composed of silicon nitride.
Claim 7
Dependent Claim 17 words
A method in accordance with claim 2 wherein said first dielectric spacers are composed of silicon nitride.
Claim 8
Dependent Claim 17 words
A method in accordance with claim 3 wherein said first dielectric spacers are composed of silicon nitride.
Claim 9
Dependent Claim 17 words
A method in accordance with claim 1 wherein said second dielectric spacers are composed of silicon oxide.
Claim 10
Dependent Claim 17 words
A method in accordance with claim 2 wherein said second dielectric spacers are composed of silicon oxide.
Claim 11
Dependent Claim 17 words
A method in accordance with claim 3 wherein said second dielectric spacers are composed of silicon oxide.
Claim 12
Dependent Claim 58 words
A method in accordance with claim 1 wherein said dielectric cap layer is composed of silicon nitride, said first dielectric spacers are composed of silicon nitride with a thickness from about 300 Å to about 700 Å, and said second dielectric spacers are composed of silicon oxide with a thickness from about 200 Å to about 800 Å.
Claim 13
Independent Claim 169 words
A method of forming a semiconductor device on a doped silicon semiconductor substrate with a pair of gate conductor stacks formed thereon, said gate conductor stacks comprising a gate oxide layer and a gate electrode layer, comprising the steps as follows: ion implanting lightly doped regions in the surface of said substrate, said lightly doped regions being self-aligned with said gate conductor stacks, forming first dielectric spacers of a first dielectric material on the sidewalls of said gate conductor stacks, forming second dielectric spacers of a second dielectric material on the sidewalls of said first dielectric spacers adjacent to said gate conductor stacks, ion implanting fully doped regions in the surface of said substrate, said fully doped regions being self-aligned with said first and second dielectric spacers formed on said gate conductor stacks, forming a blanket cap dielectric layer over said gate electrode, forming a mask with a contact opening therethrough over a contact region, etching away said second dielectric spacers below said contact opening, down to said substrate.
Claim 14
Independent Claim 169 words
A method of forming a semiconductor device on a doped silicon semiconductor substrate with a pair of gate conductor stacks formed thereon, said gate conductor stacks comprising a gate oxide layer and a gate electrode layer, comprising the steps as follows: ion implanting lightly doped regions in the surface of said substrate, said lightly doped regions being self-aligned with said gate conductor stacks, forming first dielectric spacers of a first dielectric material on the sidewalls of said gate conductor stacks, forming second dielectric spacers of a second dielectric material on the sidewalls of said first dielectric spacers adjacent to said gate conductor stacks, ion implanting fully doped regions in the surface of said substrate, said fully doped regions being self-aligned with said first and second dielectric spacers formed on said gate conductor stacks, forming a blanket cap dielectric layer over said gate electrode, forming a mask with a contact opening therethrough over a contact region, etching away said second dielectric spacers below said contact opening, down to said substrate.
Claim 15
Dependent Claim 23 words
A method in accordance with claim 12 wherein said first dielectric spacers have a thickness from about 300 Å to about 700 Å.
Claim 16
Dependent Claim 23 words
A method in accordance with claim 12 wherein said second dielectric spacers have a thickness from about 200 Å to about 800 Å.
Claim 17
Dependent Claim 23 words
A method in accordance with claim 13 wherein said second dielectric spacers have a thickness from about 200 Å to about 800 Å.
Claim 18
Dependent Claim 17 words
A method in accordance with claim 12 wherein said first dielectric spacers are composed of silicon nitride.
Claim 19
Dependent Claim 17 words
A method in accordance with claim 13 wherein said first dielectric spacers are composed of silicon nitride.
Claim 20
Dependent Claim 17 words
A method in accordance with claim 14 wherein said first dielectric spacers are composed of silicon nitride.
Claim 21
Dependent Claim 17 words
A method in accordance with claim 12 wherein said second dielectric spacers are composed of silicon oxide.
Claim 22
Dependent Claim 17 words
A method in accordance with claim 13 wherein said second dielectric spacers are composed of silicon oxide.
Claim 23
Dependent Claim 17 words
A method in accordance with claim 14 wherein said second dielectric spacers are composed of silicon oxide.
Claim 24
Dependent Claim 58 words
A method in accordance with claim 12 wherein said dielectric cap layer is composed of silicon nitride, said first dielectric spacers are composed of silicon nitride with a thickness from about 300 Å to about 700 Å, and said second dielectric spacers are composed of silicon oxide with a thickness from about 200 Å to about 800 Å.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-06-08 2001-12-08 2002-06-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-06-08 2005-12-08 2006-06-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-06-08 2009-12-08 2010-06-09 $7700.00 Window Closed / Lapsed

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