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US5761724A
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Write-invalidate cache system for a split transaction bus based shared memory multiprocessor
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-12-18
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Granted: 1998-06-02
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Expires: 2016-12-18
Abstract
Abstract A shared memory multiprocessor comprises a system bus operating under a split transaction protocol, at least one memory module coupled to the system bus and plurality of processor modules respectively having a processor and a cache. The cache maintains state information for each data block stored therein, which includes two distinct invalidated cache block states of COPYBACK-INVALID and NON-COPYBACK-INVALID. COPYBACK-INVALID and NON-COPYBACK-INVALID states commonly denote that the data block has been invalidated by another processor module in the shared memory multiprocessor. However, unlike COPYBACK-INVALID state, NON-COPYBACK-INVALID state further denotes that the processor module which most recently invalidated the data block has not copied back its updated copy of the block to the memory module, and, accordingly, the memory module does not contain the updated copy of the data block. Hence, upon an invalidation miss for a data block in a processor module, when the data block is in NON-COPYBACK-INVALID state as indicated by the state information of the data block, the processor module sends a read (with invalidation) request to other processor modules only, excluding the memory module from the read (with invalidation) request transaction.
Inventors
- 👤 Chu-Shik Jhon
- 👤 Seong-Tae Jhang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
299 words
A shared memory multiprocessor having a system bus operating under a split transaction protocol, at least one memory module coupled to the system bus and a plurality of processor modules respectively coupled to the system bus, each of the processor modules comprising: a processor; a cache coupled between the processor and the system bus for storing a number of data blocks; a state information storage associated with the cache, for storing a number of cache block states, each cache block state denoting the current state of each of data blocks stored in the cache and the cache block states including: a first invalid state in which the data block to be accessed is most recently invalidated by another processor module and the updated copy of the data block has not been copied back to the memory module; and a second invalid state in which the data block to be accessed has been invalidated by another processor module and the updated copy of the block of data has been copied back to the memory module; means, upon receiving an access request from the processor for a data block, for accessing the updated copy of the access requested data block in other processor modules by sending a cache-to-caches access request via the system bus to other processor modules, when the access requested data block is in the first invalid state, to thereby prevent the memory module responding to the cache-to-caches access request; and means, upon receiving an access request from the processor for a data block, for accessing the updated copy of the access requested data block in other processor modules by sending a broadcast access request via the system bus to other processor modules and the memory module when the access requested data block is in the second invalid state.
Claim 2
Dependent Claim
299 words
A shared memory multiprocessor having a system bus operating under a split transaction protocol, at least one memory module coupled to the system bus and a plurality of processor modules respectively coupled to the system bus, each of the processor modules comprising: a processor; a cache coupled between the processor and the system bus for storing a number of data blocks; a state information storage associated with the cache, for storing a number of cache block states, each cache block state denoting the current state of each of data blocks stored in the cache and the cache block states including: a first invalid state in which the data block to be accessed is most recently invalidated by another processor module and the updated copy of the data block has not been copied back to the memory module; and a second invalid state in which the data block to be accessed has been invalidated by another processor module and the updated copy of the block of data has been copied back to the memory module; means, upon receiving an access request from the processor for a data block, for accessing the updated copy of the access requested data block in other processor modules by sending a cache-to-caches access request via the system bus to other processor modules, when the access requested data block is in the first invalid state, to thereby prevent the memory module responding to the cache-to-caches access request; and means, upon receiving an access request from the processor for a data block, for accessing the updated copy of the access requested data block in other processor modules by sending a broadcast access request via the system bus to other processor modules and the memory module when the access requested data block is in the second invalid state.
Claim 3
Dependent Claim
74 words
The shared memory multiprocessor of claim 1, wherein the cache block states further includes a third invalid state in which the data block to be accessed is not in the cache and the processor module further comprises means, upon receiving an access request from the processor for a data block, for performing a block replacement process to send the broadcast read request via the system bus to other processor modules and the memory module.
Claim 4
Dependent Claim
112 words
The shared memory multiprocessor of claim 2, wherein the cache block states further includes: a first valid state in which the data block to be accessed has been modified; the data block to be accessed is inconsistent with that in the memory; and no other processor module has a copy of the data block in a valid state; a second valid state in which the data block to be accessed is consistent with that in the memory module; and a third valid state in which the data block to be accessed is consistent with that in the memory and no other processor module has the data block in the first valid state.
Claim 5
Dependent Claim
54 words
The shared memory multiprocessor of claim 3, wherein the processor module further comprises means, in response to the broadcast access request, for sending a memory inhibit signal for use in preventing the memory from responding to the broadcast access request, and then for providing the requested data block in one of the valid states.
Claim 6
Dependent Claim
100 words
The shared memory multiprocessor of claim 4, wherein the first invalid state includes destination information denoting said another processor module which has recently invalidated the data block to be accessed and wherein the processor module further comprises means, upon receiving an access request from the processor for a data block, for accessing the updated copy of the requested data block to be accessed in the destination processor module by sending a cache-to-cache access request via the system bus to the destination processor module designated by the destination information when the access requested data block is in the first invalid state.
Claim 7
Dependent Claim
86 words
The shared memory multiprocessor of claim 1, wherein the cache includes: a data cache for storing the data blocks; a processor tag cache for storing tag addresses of physical addresses of the data blocks; and a comparator for comparing, upon receiving an access request for a data block from the processor, a tag address of a physical address of the data block with one of the tag addresses from the processor tag caches accessed by a block address of the physical address of the data block.
Claim 8
Dependent Claim
82 words
The shared memory multiprocessor of claim 6, wherein the cache further includes: a bus monitor tag cache for storing the tag addresses; and a second comparator for comparing, upon receiving an access request for a desired block of data from one of processor modules, a tag address of a physical address of the desired data block with one of the tag addresses from the bus monitor tag caches accessed by a block address of the physical address of the desired data block.
Claim 9
Dependent Claim
14 words
The shared memory multiprocessor of claim 7, wherein the processor includes an internal cache.
Claim 10
Dependent Claim
22 words
The shared memory multiprocessor of claim 1, wherein said each of the processor modules further comprises a predetermined number of hierarchical caches.
Claim 11
Dependent Claim
38 words
The shared memory multiprocessor of claim 1, wherein said plurality of the processor modules is implemented by a preselected number of physical modules, said preselected number being equal to or smaller than the number of the processor modules.
Claim 12
Dependent Claim
23 words
The shared memory multiprocessor of claim 1, wherein said at least one memory module is distributed among said plurality of the processor modules.
Claim 13
Dependent Claim
38 words
The shared memory multiprocessor of claim 1, wherein the system bus containing an address bus, a data bus and a control bus provides communications among said at least one memory module and said plurality of the processor modules.
Claim 14
Independent Claim
279 words
A method for controlling the cache coherence in a shared memory multiprocessor having a system bus operating under a split transaction protocol, wherein at least one memory module coupled to the system bus and a plurality of processor modules respectively coupled to the system bus, each of the processor modules having a cache memory, comprising the steps of: (a) managing data blocks in the cache memories by using cache block states for denoting each data block stored in the cache memories, the cache block states containing: a first invalid state in which the data block to be accessed is most recently invalidated by another processor module and the updated copy of the data block has not copied back to the memory module; and a second invalidate state in which the data block to be accessed has been invalidated by another processor module and the updated copy of the block of data has copied back to the memory module; (b) upon receiving an access request from the processor for a data block, accessing the updated copy of the access requested data block in other processor modules by sending a cache-to-caches access request via the system bus to other processor modules when the access requested data block is in the first invalid state, the memory module not responding to the cache-to-caches access request; and (c) upon receiving an access request from the processor for a data block, accessing the updated copy of the access requested data block in other processor modules by sending a broadcast access request via the system bus to other processor modules and the memory module when the access requested data block is in the second invalid state.
Claim 15
Independent Claim
279 words
A method for controlling the cache coherence in a shared memory multiprocessor having a system bus operating under a split transaction protocol, wherein at least one memory module coupled to the system bus and a plurality of processor modules respectively coupled to the system bus, each of the processor modules having a cache memory, comprising the steps of: (a) managing data blocks in the cache memories by using cache block states for denoting each data block stored in the cache memories, the cache block states containing: a first invalid state in which the data block to be accessed is most recently invalidated by another processor module and the updated copy of the data block has not copied back to the memory module; and a second invalidate state in which the data block to be accessed has been invalidated by another processor module and the updated copy of the block of data has copied back to the memory module; (b) upon receiving an access request from the processor for a data block, accessing the updated copy of the access requested data block in other processor modules by sending a cache-to-caches access request via the system bus to other processor modules when the access requested data block is in the first invalid state, the memory module not responding to the cache-to-caches access request; and (c) upon receiving an access request from the processor for a data block, accessing the updated copy of the access requested data block in other processor modules by sending a broadcast access request via the system bus to other processor modules and the memory module when the access requested data block is in the second invalid state.
Claim 16
Dependent Claim
74 words
The method of claim 13, wherein the block states further includes a third invalid state in which the data block to be accessed is not in the cache; and further comprising the step (d) of, upon receiving an access request from the processor for a data block, performing a block replacement process for the memory module to send the broadcast read request via the system bus to other processor modules and the memory module.
Claim 17
Dependent Claim
109 words
The method of claim 14, wherein the block states further includes: a first valid state in which the data block to be accessed has been modified; the data block to be accessed is in inconsistent with that in the memory; and no other processor module has a copy of the data block in a valid state; a second valid state in which the data block to be accessed is consistent with that in the memory module; and a third valid state in which the data block to be accessed is consistent with that in the memory and no other processor module has the block in the first valid state.
Claim 18
Dependent Claim
47 words
The method of claim 15, wherein the step (d) includes the step of, upon receiving the broadcast access request, sending a memory inhibit signal for use in prohibiting the memory responding to the broadcast request to provide the requested data block in one of the valid states.
Claim 19
Dependent Claim
95 words
The method of claim 16, wherein the first invalid state includes destination information denoting said another processor module which has recently invalidated the data block to be accessed and the step (b) includes the step of, upon receiving an access request from the processor for a data block, accessing the updated copy of the access requested data block in the destination processor module by sending a cache-to-cache access request via the system bus to the destination processor module designated by the destination information when the access requested data block is in the first invalid state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |