Comparator with latch

Claim 2

A latch comprising a first comparator having an output, a first input and a second input, the first input being connected to receive a comparison signal having a high or low value and said first comparator generating a first or second state at the output depending on a comparison between the first input and the second input; and circuit means, having an input coupled to the output of said first comparator and a reset input coupled to receive a reset signal having a reset state or non-reset state, for providing a latch signal to the second input of said first comparator when the reset signal is in the non-reset state and the output from said first comparator is in the first state, the latch signal being outside of a range of voltages extending between the low value and high value of the comparison signal such that the output of said first comparator remains in the first state when the latch signal is being provided to the second input of said first comparator.

Claim 3

The latch of claim 1 wherein said circuit means provides a comparator reference signal to the second input of said first comparator if the reset signal is in the reset state or the output from said first comparator is in the second state, the comparator reference signal having a voltage between the low value and the high value of the comparison signal.

Claim 4

The latch of claim 1 wherein said circuit means comprises a second comparator for comparing a reference voltage to the higher of the reset input and the input coupled to the output of said first comparator.

Claim 5

The latch of claim 1 further comprising a level shifter connected between the output of said first comparator and said circuit means to provide a signal corresponding to the output of said first comparator having a voltage range substantially equal to a range between the reset state and the non-reset state of the reset signal.

Claim 6

A comparator with latch comprising: a first comparator having a first output, a ramp input and a control input, said comparator generating a high value signal or low value signal depending on a comparison between the ramp input and the control input; a second comparator having an output, a first input and a second input, the first input being connected to the first output of said first comparator and said second comparator generating a first or second state at its output depending on a comparison between the first input and the second input; and circuit means, having an input coupled to the output of said second comparator and a reset input coupled to receive a reset signal having a reset state or non-reset state, for providing a first latch signal to the second input of said second comparator when the reset signal is in the non-reset state and the output from said second comparator is in the first state, the first latch signal being outside of a range of voltages extending between the low value signal and the high value signal such that the output of said second comparator remains in the first state when the first latch signal is being provided to the second input of said second comparator.

Claim 7

A comparator with latch comprising: a first comparator having a first output, a ramp input and a control input, said comparator generating a high value signal or low value signal depending on a comparison between the ramp input and the control input; a second comparator having an output, a first input and a second input, the first input being connected to the first output of said first comparator and said second comparator generating a first or second state at its output depending on a comparison between the first input and the second input; and circuit means, having an input coupled to the output of said second comparator and a reset input coupled to receive a reset signal having a reset state or non-reset state, for providing a first latch signal to the second input of said second comparator when the reset signal is in the non-reset state and the output from said second comparator is in the first state, the first latch signal being outside of a range of voltages extending between the low value signal and the high value signal such that the output of said second comparator remains in the first state when the first latch signal is being provided to the second input of said second comparator.

Claim 8

The comparator with latch of claim 5 wherein said first comparator further includes a disable input connected in parallel with the control input.

Claim 9

The comparator with latch of claim 5 wherein said first comparator further comprises a second output providing a low valued signal when the first output provides a high valued signal and providing a high valued signal when the first output provides a low valued signal.

Claim 10

The comparator with latch of claim 7 further comprising a third comparator having an output, a first input and a second input, the first input being connected to the second output of said first comparator and said third comparator generating a first or second state at its output depending on a comparison between the first input and the second input and wherein said circuit means further provides a second latch signal to the second input of said third comparator when the reset signal is in the non-reset state and the output from said second comparator is in the first state, the second latch signal being outside of a range of voltages extending between the low value signal and the high value signal such that the output of said third comparator remains latched when the second latch signal is being provided to the second input of said third comparator.

Claim 11

The comparator with latch of claim 8 wherein the first latch signal is below the low value signal and the second latch signal is above the high value signal.

Claim 12

The comparator with latch of claim 8 further comprising a fourth comparator having an output, a first input connected to the output of said second comparator and a second input connected to the output of said third comparator wherein the output of said fourth comparator is latched high when said circuit means is providing the first and second latch signals.

Claim 13

The comparator with latch of claim 5 further comprising a fifth comparator for comparing the ramp signal to a reference threshold and for preventing the reset state while the ramp signal remains above the reference threshold.

Claim 14

The comparator with latch of claim 5 wherein said circuit means provides a comparator reference signal to the second input of said second comparator if the reset signal is in the reset state or the output from said second comparator is in the second state, the comparator reference signal having a voltage between the low value signal and the high value signal.

Claim 15

The comparator with latch of claim 5 wherein said circuit means comprises a comparator for comparing a reference voltage to the higher of the reset input and the input coupled to the output of said second comparator.

Claim 16

The comparator with latch of claim 5 further comprising a level shifter connected between the output of said second comparator and said circuit means to provide a signal corresponding to the output of said second comparator having a voltage range substantially equal to a range between the reset state and the non-reset state of the reset signal.

Claim 17

A latchable comparator comprising: a comparator having a switch output, a set output, a ramp input, a control input, a first reference input and a second reference input, said comparator generating a first state on the switch output and the set output when the ramp input exceeds the control input, maintaining the first state when latch signals are received on the first and second reference inputs and generating a second state on the switch output and the set output in the absence of the latch signals when the ramp input falls below the control input; and flip flop means having a set input connected to the first output of said comparator, a reset input and latching outputs connected to the first and second reference inputs of said comparator, said flip flop means generating the latch signals on the latching outputs when the reset input is in the non-reset state and said comparator is generating the first state and maintaining the latch signals until a reset signal is received on the reset input.

Claim 18

A latchable comparator comprising: a comparator having a switch output, a set output, a ramp input, a control input, a first reference input and a second reference input, said comparator generating a first state on the switch output and the set output when the ramp input exceeds the control input, maintaining the first state when latch signals are received on the first and second reference inputs and generating a second state on the switch output and the set output in the absence of the latch signals when the ramp input falls below the control input; and flip flop means having a set input connected to the first output of said comparator, a reset input and latching outputs connected to the first and second reference inputs of said comparator, said flip flop means generating the latch signals on the latching outputs when the reset input is in the non-reset state and said comparator is generating the first state and maintaining the latch signals until a reset signal is received on the reset input.

Claim 19

The latchable comparator of claim 15 further comprising a second comparator having a reference threshold input and an input coupled to the ramp input of said comparator for comparing the ramp signal to a reference threshold and for preventing the reset signal while the ramp signal remains above the reference threshold.

Claim 20

The latchable comparator of claim 15 wherein said comparator further includes a disable input connected in parallel with the control input.

Claim 23

The method of claim 18 further comprising steps of providing a comparator reference signal to the second input if the reset input is in the reset state or if the second state is being generated, the comparator reference signal having a voltage between the low value and the high value of the comparison signal.

Claim 24

The method of claim 18 further comprising steps of comparing a reference voltage to the higher of the reset input and an input coupled to the output of the comparator.