Timing signal generating circuit

Claim 2

A timing signal generating circuit comprising: a first reference voltage; a second reference voltage; a third reference voltage; a circuit including a switch, a first resistor and a second resistor connected in series between the first and second reference voltages; a first pulse generating circuit to which a trigger signal is supplied, said first pulse generating circuit generating a pulse for changing a condition of said switch for a predetermined period from a time when the trigger signal is supplied; an operational amplifier which has a first input terminal connected to a node between said first and second resistors and to an output terminal of said operational amplifier through a capacitor, and a second input terminal coupled to said third reference voltage; a clamping circuit which allows an output voltage of said operational amplifier to vary while said capacitor is being charged and discharged, said clamping circuit clamping the output voltage of the operational amplifier to a predetermined voltage value while the capacitor is not being charged or discharged; and a second pulse generating circuit which generates as a timing signal a pulse having a width corresponding to a period during which the output voltage of the operational amplifier varies from the predetermined voltage value.

Claim 3

A timing signal generating circuit according to claim 1, wherein said first pulse generating circuit generates a pulse for a changeover of said switch between a condition where either of said first and second resistors is activated and a condition where both of the first and second resistors are activated.

Claim 4

A timing signal generating circuit according to claim 1, wherein said first reference voltage is a ground potential and wherein said third reference voltage is obtained by dividing the second reference voltage through a plurality of resistors.

Claim 5

A timing signal generating circuit according to claim 1, wherein said clamping circuit has a transistor having an emitter connected to one end of the capacitor and a base connected to another end of the capacitor, wherein a collector of said transistor is connected to ground through a resistor, and wherein a voltage generated at said collector is supplied to the second pulse generating circuit.

Claim 6

A floppy disk drive apparatus having a timing signal generating circuit, said timing signal generating circuit comprising: a first reference voltage; a second reference voltage; a third reference voltage; a circuit including a switch, a first resistor and a second resistor connected in series between the first and second reference voltages; a first pulse generating circuit to which a trigger signal is supplied, said first pulse generating circuit generating a pulse for changing a condition of said switch for a predetermined period from a time when the trigger signal is supplied; an operational amplifier which has a first input terminal connected to a node between said first and second resistors and to an output terminal of said operational amplifier through a capacitor, and a second input terminal coupled to said third reference voltage; a clamping circuit which allows an output voltage of said operational amplifier to vary while said capacitor is being charged and discharged, said clamping circuit clamping the output voltage of the operational amplifier to a predetermined voltage value while the capacitor is not being charged or discharged; and a second pulse generating circuit which generates as a timing signal a pulse having a width corresponding to a period during which the output voltage of the operational amplifier varies from the predetermined voltage value.

Claim 7

A floppy disk drive apparatus having a timing signal generating circuit, said timing signal generating circuit comprising: a first reference voltage; a second reference voltage; a third reference voltage; a circuit including a switch, a first resistor and a second resistor connected in series between the first and second reference voltages; a first pulse generating circuit to which a trigger signal is supplied, said first pulse generating circuit generating a pulse for changing a condition of said switch for a predetermined period from a time when the trigger signal is supplied; an operational amplifier which has a first input terminal connected to a node between said first and second resistors and to an output terminal of said operational amplifier through a capacitor, and a second input terminal coupled to said third reference voltage; a clamping circuit which allows an output voltage of said operational amplifier to vary while said capacitor is being charged and discharged, said clamping circuit clamping the output voltage of the operational amplifier to a predetermined voltage value while the capacitor is not being charged or discharged; and a second pulse generating circuit which generates as a timing signal a pulse having a width corresponding to a period during which the output voltage of the operational amplifier varies from the predetermined voltage value.