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US4733104A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit for controlling power converter by frequency modulation and pulse width modulation

Assignee: Intersil Corp
•
Filing: 1987-05-04
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Granted: 1988-03-22
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Expires: 2007-05-04
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Abstract

Abstract An integrated circuit contains the gate drivers and the control components for constructing a DC power supply in any of the most popular converter topologies. Multi-function elements in the control circuit minimize the area of the chip. The integrated circuit drives both the upper and lower switches of a half-bridge converter and separately regulates two power supply output voltages, one by pulse width modulation and the other by frequency modulation.

Inventors

  • 👤 Robert L. Steigerwald
  • 👤 Keku M. Mistry

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 14:36
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/337; H02M3/3376; H02M3/33561

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 308 words
An integrated circuit comprising: voltage-controlled oscillator means for providing a variable frequency VCO signal in response to an external input signal; a first flip-flop having an input and a pair of complementary outputs, said flip-flop input being connected to the output of said voltage-controlled oscillator means; a first two-input AND gate for providing a turn-on pulse and having one input connected to one of said flip-flop outputs; a second two-input AND gate for providing a turn-on pulse and having one input connected to the other of said flip-flop outputs; amplifier means for receiving an input signal and providing an output signal, a first comparator having one input coupled to the output of said amplifier means and having its other input coupled to the output of said voltage-controlled oscillator means, the output of said first comparator being coupled to the remaining inputs of said first and second AND gates; a third AND gate having an input responsive to an enable signal; a fourth AND gate having an input responsive to said enable signal; a first dead-time circuit coupling the output of said first AND gate to an input of said third AND gate, said first dead-time circuit delaying the beginning of each turn-on pulse from said first AND gate by a first predetermined dead-time; a second dead-time circuit coupling the output of said second AND gate to an input of said fourth AND gate, said second dead-time circuit delaying the beginning of each turn-on pulse from said second AND gate by a second predetermined dead-time; and a driver circuit connected to the outputs of said third and fourth AND gates, said driver circuit having outputs adapted to drive a pair of series-connected converter switches, said driver circuit adapted to be coupled to an external capacitor for providing a voltage sufficient to drive the upper one of said converter switches.
Claim 2
Dependent Claim 308 words
An integrated circuit comprising: voltage-controlled oscillator means for providing a variable frequency VCO signal in response to an external input signal; a first flip-flop having an input and a pair of complementary outputs, said flip-flop input being connected to the output of said voltage-controlled oscillator means; a first two-input AND gate for providing a turn-on pulse and having one input connected to one of said flip-flop outputs; a second two-input AND gate for providing a turn-on pulse and having one input connected to the other of said flip-flop outputs; amplifier means for receiving an input signal and providing an output signal, a first comparator having one input coupled to the output of said amplifier means and having its other input coupled to the output of said voltage-controlled oscillator means, the output of said first comparator being coupled to the remaining inputs of said first and second AND gates; a third AND gate having an input responsive to an enable signal; a fourth AND gate having an input responsive to said enable signal; a first dead-time circuit coupling the output of said first AND gate to an input of said third AND gate, said first dead-time circuit delaying the beginning of each turn-on pulse from said first AND gate by a first predetermined dead-time; a second dead-time circuit coupling the output of said second AND gate to an input of said fourth AND gate, said second dead-time circuit delaying the beginning of each turn-on pulse from said second AND gate by a second predetermined dead-time; and a driver circuit connected to the outputs of said third and fourth AND gates, said driver circuit having outputs adapted to drive a pair of series-connected converter switches, said driver circuit adapted to be coupled to an external capacitor for providing a voltage sufficient to drive the upper one of said converter switches.
Claim 3
Dependent Claim 74 words
The integrated circuit of claim 1 further comprising: a second comparator responsive to a pair of external input signals; a second flip-flop coupled to said second comparator and the output of said voltage-controlled oscillator means, said second flip-flop adapted to be reset by said second comparator and adapted to be set by said voltage-controlled oscillator means, the output of said second flip-flop being connected to separate inputs of said third and fourth AND gates.
Claim 4
Dependent Claim 108 words
The integrated circuit of claim 1 further comprising a protection circuit including: sensing means for detecting whether predetermined parameters exceed predetermined limits; a third flip-flop coupled to said sensing means for switching from an initial state to a disable state when said sensing means indicates that one of said predetermined parameters has exceeded its predetermined limits, said third flip-flop being reset to said initial state in response to a reset signal; and disabling means coupled to said third flip-flop and to said third and fourth AND gates for removing said enable signal from said third and fourth AND gates when said third flip-flop is in said disable state.
Claim 5
Dependent Claim 21 words
The integrated circuit of claim 1 further comprising prising a voltage regulator for supplying regulated DC voltage for said integrated circuit.
Claim 6
Dependent Claim 37 words
The integrated circuit of claim 1 further comprising additional amplifier means for receiving an input signal and for providing an externally available output signal, said additional amplifier means adapted to the coupled to said voltage-controlled oscillator means.

References Cited (Backward Citations)

US4061930A Cited
US4188547A Cited
US4125814A Cited
US4146801A Cited
US4494134A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-03-22 1991-09-21 1992-03-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-03-22 1995-09-21 1996-03-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-03-22 1999-09-21 2000-03-22 $7700.00 Window Closed / Lapsed

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