Ferroelectric memory having pair of reference cells

Claim 2

A ferroelectric memory, comprising: at least one word line, a bit line, a reference word line, a reference bit line, at least one memory cell comprising a first transmission transistor with a first terminal connected to the bit line and a gate connected to the word line, and a ferroelectric capacitor for storing data connected between a second terminal of the first transmission transistor and a plate electrode, a first reference cell comprising a second transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, and a first reference data storing ferroelectric capacitor for storing first reference data, said first reference data storing ferroelectric capacitor being connected between a second terminal of the second transmission transistor and a first reference plate electrode, and a second reference cell comprising a third transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, and a second reference data storing ferroelectric capacitor for storing second reference data having a reverse phase from the first reference data, said second reference data storing ferroelectric capacitor being connected between a second terminal of the third transmission transistor and a second reference plate electrode; wherein said first and second reference data storing capacitors have an area which is one half an area of said ferroelectric capacitor of said at least one memory cell.

Claim 3

A ferroelectric memory according to claim 1, further comprising a sense amplifier connected to said bit line and said reference bit line for comparing a potential of the read bit line and a potential of the reference bit line during a read operation, and determining content of said at least one memory cell in response to said comparison.

Claim 4

A ferroelectric memory, comprising: at least one word line, a bit line, a reference word line, a reference bit line, at least one memory cell comprising a first transmission transistor with a first terminal connected to the bit line and a gate connected to the word line, and a ferroelectric capacitor for storing data connected between a second terminal of the first transmission transistor and a plate electrode, a first reference cell comprising a second transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, and a first reference data storing ferroelectric capacitor for storing first reference data, said first reference data storing ferroelectric capacitor being connected between a second terminal of the second transmission transistor and a first reference plate electrode, a second reference cell comprising a third transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, and a second reference data storing ferroelectric capacitor for storing second reference data having a reverse phase from the first reference data, said second reference data storing ferroelectric capacitor being connected between a second terminal of the third transmission transistor and a second reference plate electrode, and a switch for connecting an additional capacitance to the reference bit line at the time of a read operation.

Claim 5

A ferroelectric memory, comprising: at least one word line, a bit line, a reference word line, a reference bit line, at least one memory cell comprising a first transmission transistor with a first terminal connected to the bit line and a gate connected to the word line, and a ferroelectric capacitor for storing data connected between a second terminal of the first transmission transistor and a plate electrode, a first reference cell comprising a second transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, and a first reference data storing ferroelectric capacitor for storing first reference data, said first reference data storing ferroelectric capacitor being connected between a second terminal of the second transmission transistor and a first reference plate electrode, a second reference cell comprising a third transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, and a second reference data storing ferroelectric capacitor for storing second reference data having a reverse phase from the first reference data, said second reference data storing ferroelectric capacitor being connected between a second terminal of the third transmission transistor and a second reference plate electrode, and a switch for connecting an additional capacitance to the reference bit line at the time of a read operation.

Claim 6

A ferroelectric memory according to claim 3, wherein the ferroelectric capacitor of the at least one memory cell is equal in size to the ferroelectric capacitors of the first and second reference cells.

Claim 7

A ferroelectric memory according to claim 3, wherein: the ferroelectric memory comprises a plurality of memory arrays each comprising a word line, a bit line, a reference word line, a reference bit line, a memory cell and first and second reference cells; and said additional capacitance is a capacitance of a bit line of a non-selected memory array.

Claim 8

A ferroelectric memory according to claim 3, further comprising a second switch for connecting a second additional capacitance to said bit line at a time of a read operation.

Claim 9

A ferroelectric memory according to claim 3, further comprising a sense amplifier connected to said bit line and said reference bit line for comparing a potential of the read bit line and a potential of the reference bit line during a read operation, and determining content of said at least one memory cell in response to said comparison.

Claim 10

A ferroelectric memory according to claim 3, wherein said additional capacitance is equal to a capacitance of said bit line.

Claim 11

A ferroelectric memory according to claim 5, wherein said additional capacitance causes a total capacitance of said reference bit line to be twice a capacitance of said bit line.

Claim 12

A ferroelectric memory according to claim 3, wherein said switch is a transistor.

Claim 13

A ferroelectric memory according to claim 3, wherein said additional capacitance is a capacitor connected between said switch and ground.

Claim 14

A ferroelectric memory, comprising; at least one word line; a bit line; a reference word line; a reference bit line; at least one memory cell comprising a first transmission transistor with a first terminal connected to the bit line and a gate connected to the word line, and a ferroelectric capacitor for storing data connected between a second terminal of the first transmission transistor and a plate electrode; a first reference cell comprising a second transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, a first reference data storing ferroelectric capacitor for storing first reference data connected between a second terminal of the second transmission transistor and a first reference plate electrode, and a first connecting means for connecting a first connection point of the second transmission transistor and the first reference data storing ferroelectric capacitor to a predetermined first potential; a second reference cell comprising a third transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, a second reference data storing ferroelectric capacitor for storing second reference data having a reverse phase from the first reference data connected between the first terminal of the third transmission transistor and a second reference plate electrode, and a second connecting means for connected a second connection point of the third transmission transistor and the second reference data storing ferroelectric capacitor to a predetermined second potential; and means for writing the first reference data into the first reference cell by connecting the first connection point to the first potential and writing the second reference data into the second reference cell by connecting the second connection point to the second potential.

Claim 15

A ferroelectric memory, comprising; at least one word line; a bit line; a reference word line; a reference bit line; at least one memory cell comprising a first transmission transistor with a first terminal connected to the bit line and a gate connected to the word line, and a ferroelectric capacitor for storing data connected between a second terminal of the first transmission transistor and a plate electrode; a first reference cell comprising a second transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, a first reference data storing ferroelectric capacitor for storing first reference data connected between a second terminal of the second transmission transistor and a first reference plate electrode, and a first connecting means for connecting a first connection point of the second transmission transistor and the first reference data storing ferroelectric capacitor to a predetermined first potential; a second reference cell comprising a third transmission transistor with a first terminal connected to the reference bit line and a gate connected to the reference word line, a second reference data storing ferroelectric capacitor for storing second reference data having a reverse phase from the first reference data connected between the first terminal of the third transmission transistor and a second reference plate electrode, and a second connecting means for connected a second connection point of the third transmission transistor and the second reference data storing ferroelectric capacitor to a predetermined second potential; and means for writing the first reference data into the first reference cell by connecting the first connection point to the first potential and writing the second reference data into the second reference cell by connecting the second connection point to the second potential.

Claim 16

A ferroelectric memory according to claim 12, further comprising a sense amplifier connected to said bit line and said reference bit line for comparing a potential of the read bit line and a potential of the reference bit line during a read operation, and determining content of said at least one memory cell in response to said comparison.