Data storage element and method for reading data therefrom

Claim 2

A data storage element, comprising: a first memory cell having a control terminal, a data terminal, and a cell plate terminal, wherein the control terminal is coupled for receiving a first memory control signal, the data terminal is coupled for transmitting a data signal, and the cell plate terminal is coupled for receiving a first extraction signal; and a first reference which comprises: a first reference capacitor with polarization retention having a first electrode and a second electrode, the first electrode coupled for receiving a second extraction signal; a first switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled for receiving a first reset signal, the first current conducting electrode is coupled to the second electrode of the first reference capacitor, and the second current conducting electrode is coupled to a first voltage supply conductor; a second switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled for receiving a first reference control signal, the first current conducting electrode is coupled to the second electrode of the first reference capacitor, and the second current conducting electrode is coupled for transmitting a reference signal; a second reference capacitor with polarization retention having a first electrode and a second electrode, the first electrode coupled for receiving the second extraction signal; a third switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled for receiving a second reset signal, the first current conducting electrode is coupled to the second electrode of the second reference capacitor, and the second current conducting electrode is coupled to a second voltage supply conductor; and a fourth switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled to the control electrode of the second switch, the first current conducting electrode is coupled to the second electrode of the second reference capacitor, and the second current conducting electrode is coupled to the second current conducting electrode of the second switch.

Claim 3

The data storage element of claim 1, wherein the first memory cell comprises: a ferroelectric capacitor having a first electrode and a second electrode, the first electrode serving as the cell plate terminal of the first memory cell; and a pass gate having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode serves as the control terminal of the first memory cell, the first current conducting electrode is coupled to the second electrode Of the ferroelectric capacitor of the first memory cell, and the second current conducting electrode serves as the data terminal of the first memory cell.

Claim 4

The data storage element of claim 2, wherein the pass gate, the first switch, the second switch, the third switch, and the fourth switch are field effect transistors.

Claim 5

The data storage element of claim 2, wherein the first reference capacitor and the second reference capacitor are ferroelectric capacitors, and a capacitance of the first reference capacitor and a capacitance of the second reference capacitor are equal to a capacitance of the ferroelectric capacitor of the first memory cell.

Claim 6

The data storage element of claim 1, further comprising a sense amplifier having a first terminal and a second terminal, the first terminal coupled to the data terminal of the first memory cell and the second terminal coupled to the second current conducting electrode of the second switch.

Claim 7

The data storage element of claim 5, further comprising: a second memory cell having a control terminal, a data terminal, and a cell plate terminal, wherein the control terminal is coupled for receiving a second memory control signal, the data terminal is coupled to the second terminal of the sense amplifier, and the cell plate terminal is coupled for receiving the first extraction signal; a reference capacitance line; a first coupling switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled for receiving the first reference control signal, the first current conducting electrode is coupled to the reference capacitance line, and the second current conducting electrode is coupled to the second terminal of the sense amplifier; and a second coupling switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled for receiving a second reference control signal, the first current conducting electrode is coupled to the reference capacitance line, and the second current conducting electrode is coupled to the first terminal of the sense amplifier.

Claim 8

The data storage element of claim 6, further comprising: a fifth switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, the control electrode coupled for receiving the second reference control signal, the first current conducting electrode coupled to the second electrode of the first reference capacitor, and the second current conducting electrode coupled to the first terminal of the sense amplifier; and a sixth switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, the control electrode coupled to the control electrode of the fifth switch, the first current conducting electrode coupled to the second electrode of the second reference capacitor, and the second current conducting electrode coupled to the second current conducting electrode of the fifth switch.

Claim 9

The data storage element of claim 6, further comprising a second reference cell which comprises: a third reference capacitor with polarization retention having a first electrode and a second electrode, the first electrode coupled for receiving the second extraction signal; a fifth switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled to the control electrode of the first switch, the first current conducting electrode is coupled to the second electrode of the third reference capacitor, and the second current conducting electrode is coupled to the first voltage supply conductor; a sixth switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled for receiving the second reference control signal, the first current conducting electrode is coupled to the second electrode of the third reference capacitor, and the second current conducting electrode is coupled to the first terminal of the sense amplifier; a fourth reference capacitor with polarization retention having a first electrode and a second electrode, the first electrode coupled for receiving the second extraction signal; a seventh switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled to the control electrode of the third switch, the first current conducting electrode is coupled to the second electrode of the fourth reference capacitor, and the second current conducting electrode is coupled to the second voltage supply conductor; and an eighth switch having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode is coupled to the control electrode of the sixth switch, the first current conducting electrode is coupled to the second electrode of the fourth reference capacitor, and the second current conducting electrode is coupled to the second current conducting electrode of the sixth switch.

Claim 10

A memory unit having first and second word lines, first and second arrays of bit lines, and a plate line, comprising: a first array of memory cells, a memory cell in the first array of memory cells having a control terminal coupled to the first word line, a data terminal coupled to a corresponding bit line in the first array of bit lines, and a cell plate terminal coupled to the plate line, wherein the memory cell includes: a capacitor with polarization retention having a first electrode and a second electrode, the first electrode serving as the cell plate terminal of the memory cell; and a pass gate having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode serves as the control terminal of the memory cell, the first current conducting electrode is coupled to the second electrode of the capacitor, and the second current conducting electrode serves as the data terminal of the memory cell; a second array of memory cells, a memory cell in the second array of memory cells having a control terminal coupled to the second word line, a data terminal coupled to a corresponding bit line in the second array of bit lines, and a cell plate terminal coupled to the plate line; a plurality of sense amplifiers, a sense amplifier of the plurality of sense amplifiers having a first terminal coupled to the corresponding bit line in the first array of bit lines and a second terminal coupled to the corresponding bit line in the second array of bit lines; a plurality of reference capacitance lines; a first array of switches, a switch in the first array of switches having a control electrode coupled for receiving a first reference control signal, a first current conducting electrode coupled to a corresponding reference capacitance line of the plurality of reference capacitance lines, and a second current conducting electrode coupled to the corresponding bit line in the second array of bit lines; a second array of switches, a switch in the second array of switches having a control electrode coupled for receiving a second reference control signal, a first current conducting electrode coupled to the corresponding reference capacitance line, and a second current conducting electrode coupled to the corresponding bit line in the first array of bit lines; a first set of reference capacitors with polarization retention, a reference capacitor in the first set of reference capacitors having a first electrode coupled for receiving a reference extraction signal and a second electrode; a first set of switches, a switch in the first set of switches having a control electrode coupled for receiving a first reset signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the first set of reference capacitors, and a second current conducting electrode coupled to a first voltage supply conductor; a second set of switches, a switch in the second set of switches having a control electrode coupled for receiving the first reference control signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the first set of reference capacitors, and a second current conducting electrode coupled to the corresponding bit line in the second array of bit lines; a second set of reference capacitors with polarization retention, a reference capacitor in the second set of reference capacitors having a first electrode coupled for receiving the reference extraction signal and a second electrode; a third set of switches, a switch in the third set of switches having a control electrode coupled for receiving a second reset signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the second set of reference capacitors, and a second current conducting electrode coupled to a second voltage supply conductor; and a fourth set of switches, a switch in the fourth set of switches having a control electrode coupled for receiving the first reference control signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the second set of reference capacitors, and a second current conducting electrode coupled to the corresponding bit line in the second array of bit lines.

Claim 11

A memory unit having first and second word lines, first and second arrays of bit lines, and a plate line, comprising: a first array of memory cells, a memory cell in the first array of memory cells having a control terminal coupled to the first word line, a data terminal coupled to a corresponding bit line in the first array of bit lines, and a cell plate terminal coupled to the plate line, wherein the memory cell includes: a capacitor with polarization retention having a first electrode and a second electrode, the first electrode serving as the cell plate terminal of the memory cell; and a pass gate having a control electrode, a first current conducting electrode, and a second current conducting electrode, wherein the control electrode serves as the control terminal of the memory cell, the first current conducting electrode is coupled to the second electrode of the capacitor, and the second current conducting electrode serves as the data terminal of the memory cell; a second array of memory cells, a memory cell in the second array of memory cells having a control terminal coupled to the second word line, a data terminal coupled to a corresponding bit line in the second array of bit lines, and a cell plate terminal coupled to the plate line; a plurality of sense amplifiers, a sense amplifier of the plurality of sense amplifiers having a first terminal coupled to the corresponding bit line in the first array of bit lines and a second terminal coupled to the corresponding bit line in the second array of bit lines; a plurality of reference capacitance lines; a first array of switches, a switch in the first array of switches having a control electrode coupled for receiving a first reference control signal, a first current conducting electrode coupled to a corresponding reference capacitance line of the plurality of reference capacitance lines, and a second current conducting electrode coupled to the corresponding bit line in the second array of bit lines; a second array of switches, a switch in the second array of switches having a control electrode coupled for receiving a second reference control signal, a first current conducting electrode coupled to the corresponding reference capacitance line, and a second current conducting electrode coupled to the corresponding bit line in the first array of bit lines; a first set of reference capacitors with polarization retention, a reference capacitor in the first set of reference capacitors having a first electrode coupled for receiving a reference extraction signal and a second electrode; a first set of switches, a switch in the first set of switches having a control electrode coupled for receiving a first reset signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the first set of reference capacitors, and a second current conducting electrode coupled to a first voltage supply conductor; a second set of switches, a switch in the second set of switches having a control electrode coupled for receiving the first reference control signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the first set of reference capacitors, and a second current conducting electrode coupled to the corresponding bit line in the second array of bit lines; a second set of reference capacitors with polarization retention, a reference capacitor in the second set of reference capacitors having a first electrode coupled for receiving the reference extraction signal and a second electrode; a third set of switches, a switch in the third set of switches having a control electrode coupled for receiving a second reset signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the second set of reference capacitors, and a second current conducting electrode coupled to a second voltage supply conductor; and a fourth set of switches, a switch in the fourth set of switches having a control electrode coupled for receiving the first reference control signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the second set of reference capacitors, and a second current conducting electrode coupled to the corresponding bit line in the second array of bit lines.

Claim 12

The memory unit of claim 9, further comprising: a third set of reference capacitors with polarization retention, a reference capacitor in the third set of reference capacitors having a first electrode coupled for receiving the reference extraction signal and a second electrode; a fifth set of switches, a switch in the fifth set of switches having a control electrode coupled for receiving the first reset signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the third set of reference capacitors, and a second current conducting electrode coupled to the first voltage supply conductor; a sixth set of switches, a switch in the sixth set of switches having a control electrode coupled for receiving the second reference control signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the third set of reference capacitors, and a second current conducting electrode coupled to the corresponding bit line in the first array of bit lines; a fourth set of reference capacitors with polarization retention, a reference capacitor in the fourth set of reference capacitors having a first electrode coupled for receiving the reference extraction signal and a second electrode; a seventh set of switches, a switch in the seventh set of switches having a control electrode coupled for receiving the second reset signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the fourth set of reference capacitors, and a second current conducting electrode coupled to the second voltage supply conductor; and an eighth set of switches, a switch in the eighth set of switches having a control electrode coupled to the control electrode of the switch in the sixth set of switches, a first current conducting electrode coupled to the second electrode of the reference capacitor in the fourth set of reference capacitors, and a second current conducting electrode coupled to the second current conducting electrode of the switch in the sixth set of switches.

Claim 13

The memory unit of claim 9, further comprising: a fifth set of switches, a switch in the fifth set of switches having a control electrode, a first current conducting electrode, and a second current conducting electrode, the control electrode coupled for receiving the second reference control signal, the first current conducting electrode coupled to the second electrode of the reference capacitor in the first set of reference capacitors, and the second current conducting electrode coupled to the corresponding bit line in the first array of bit lines; and a sixth set of switches, a switch in the sixth set of switches having a control electrode, a first current conducting electrode, and a second current conducting electrode, the control electrode coupled to the control electrode of the switch in the fifth set of switches, the first current conducting electrode coupled to the second electrode of the reference capacitor in the second set of reference capacitors, and the second current conducting electrode coupled to second current conducting electrode of the switch in the fifth set of switches.

Claim 14

The memory unit of claim 9, wherein the second current conducting electrode of the switch in the second set of switches is coupled to the corresponding bit line in the second array of bit lines via the first and second current conducting electrodes of the switch in the first array of switches and coupled to the corresponding bit line in the first array of bit lines via the first and second current conducting electrodes of the switch in the second array of switches, and wherein the control electrode of the switch in the second set of switches is further coupled for receiving the second reference control signal.

Claim 15

The memory unit of claim 12, wherein the second current conducting electrode of the switch in the fourth set of switches is coupled to the corresponding bit line in the second array of bit lines via the first and second current conducting electrodes of the switch in the first array of switches and coupled to the corresponding bit line in the first array of bit lines via the first and second current conducting electrodes of the switch in the second array of switches, and wherein the control electrode of the switch in the fourth set of switches is further coupled for receiving the second reference control signal.

Claim 16

The memory unit of claim 12, further comprising a fifth set of switches, a switch in the fifth set of switches having a control electrode coupled for receiving the second reference control signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the second set of reference capacitors, and a second current conducting electrode coupled to the corresponding bit line in the first array of bit lines.

Claim 17

The memory unit of claim 12, further comprising: a third set of reference capacitors with polarization retention, a reference capacitor in the third set of reference capacitors having a first electrode coupled for receiving the reference extraction signal and a second electrode; a fifth set of switches, switch in the fifth set of switches having a control electrode coupled for receiving the second reset signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the third set of reference capacitors, and a second current conducting electrode coupled to the second voltage supply conductor; and a sixth set of switches, a switch in the sixth set of switches having a control electrode coupled for receiving the second reference control signal, a first current conducting electrode coupled to the second electrode of the reference capacitor in the third set of reference capacitors, and a second current conducting electrode coupled to the corresponding bit line in the first array of bit lines.

Claim 20

The method for reading data from a non-volatile memory unit as claimed in claim 16, wherein the steps of placing the first reference capacitor in a first polarization state and placing the second reference capacitor in a second polarization include the steps of: applying a first voltage across first and second electrodes of the first reference capacitor, the first voltage having a first polarity; removing the first voltage applied across the first and second electrodes of the first reference capacitor; applying a second voltage across first and second electrodes of the second reference capacitor, the second voltage having a second polarity opposite to the first polarity; and removing the second voltage applied across the first and second electrodes of the second reference capacitor.

Claim 21

The method for reading data from a non-volatile memory unit as claimed in claim 17, wherein the step of removing the first voltage applied across the first and second electrodes of the first reference capacitor further includes the step of discharging the first reference capacitor and wherein the step of removing the second voltage applied across the first and second electrodes of the second reference capacitor further includes the step of discharging the second reference capacitor.

Claim 22

The method for reading data from a non-volatile memory unit as claimed in claim 16, further comprising the step of applying a potential to the first bit line and the second bit line.

Claim 23

The method for reading data from a non-volatile memory unit as claimed in claim 16, wherein the step of restoring the logic value in the non-volatile memory unit further includes the step of decoupling the first electrodes of the first and second reference capacitors from the second bit line.