Memory device with current mirror type sense amplifiers for comparing units of reference cells and information cells

Claim 1

A memory device with current mirror type sense amplifiers, comprising: a plurality of information memory cell units arranged in a matrix pattern having a predetermined number of columns and a predetermined number of rows, each of said information memory cell units comprising a first selection cell and information memory cells, information being stored in said information memory cells; a plurality of address decoder units each comprising a selector for controlling turning-on and off of said first selection cell and an address decoder for accessing said information memory cells, said selector being connected in each row to said selection cell by a selection line, and said address decoder being connected at outputs in said each row to said information memory cells by word lines; a plurality of sense amplifiers connected to columns of said information memory cell units by digit lines, respectively; and a plurality of reference memory cell units each comprising a second selection cell and reference memory cells including depletion-type NMOS transistors, and connected to rows of said information memory cell units, respectively, such that said second selection cell is connected in said each row to said selector by said selection line, and said reference memory cells are connected in said each row to said outputs of said address decoder by said word lines, whereby one of said reference memory cell units applies a reference voltage to a reference voltage line connected to said sense amplifiers, when said second selection cell is selected in said one of said reference memory cell units by said selector of said address decoder unit.