US5029138A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier circuit coupled to a bit line pair for increasing a difference in voltage level at an improved speed
Assignee: NEC Corp
•
Filing: 1990-08-13
•
Granted: 1991-07-02
•
Expires: 2010-08-13
Abstract
Abstract A sense amplifier circuit is associated with at least one memory cell and comprises a series combination of a first p-channel type transistor and a second n-channel type transistor coupled between a source of positive voltage level and a first input node, a first negative feedback loop coupled between the first input node and the second n-channel type transistor, a series combination of a third p-channel type transistor and a fourth n-channel type transistor coupled between the source of positive voltage level and a second input node, a second negative feedback loop coupled between the second input node and the fourth n-channel type transistor, an output circuit coupled to the first and third n-channel type transistors in a current-mirror fashion and producing an output data signal, and first and second load elements respectively coupled between the first and second input nodes and a ground node, wherein each of the first and second load elements is smaller in conductance than the memory cell and restricts the associated input node to excessively fluctuate upon a change of memory cell to be accessed.
Inventors
- 👤 Shinichi Iwashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:30
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
234 words
A sense amplifier circuit associated with at least one memory cell, comprising: a) a pair of input nodes respectively coupled to a signal line and a complementary signal line, said signal line and said complementary signal line being varied in voltage level in a complementary manner depending upon a bit of data information memorized in said memory cell; b) a series combination of a first transistor of one channel conductivity type and a second transistor of the opposite channel conductivity type coupled between a first source of voltage level and one of said input nodes; c) a first negative feedback loop coupled between said one of said input nodes and said second transistor; d) a series combination of a third transistor of said one channel conductivity type and a fourth transistor of said opposite channel conductivity type coupled between said first source of voltage level and the other input node; e) a second negative feedback loop coupled between the other input node and said fourth transistor; f) an output circuit coupled to said first and third transistors in a current-mirror fashion and producing an output data signal; and g) first and second load means respectively coupled between said input nodes and a second source of voltage level different in voltage level from said first source of voltage level, each of said first and second load means being smaller in conductance than said memory cell.
Claim 2
Dependent Claim
234 words
A sense amplifier circuit associated with at least one memory cell, comprising: a) a pair of input nodes respectively coupled to a signal line and a complementary signal line, said signal line and said complementary signal line being varied in voltage level in a complementary manner depending upon a bit of data information memorized in said memory cell; b) a series combination of a first transistor of one channel conductivity type and a second transistor of the opposite channel conductivity type coupled between a first source of voltage level and one of said input nodes; c) a first negative feedback loop coupled between said one of said input nodes and said second transistor; d) a series combination of a third transistor of said one channel conductivity type and a fourth transistor of said opposite channel conductivity type coupled between said first source of voltage level and the other input node; e) a second negative feedback loop coupled between the other input node and said fourth transistor; f) an output circuit coupled to said first and third transistors in a current-mirror fashion and producing an output data signal; and g) first and second load means respectively coupled between said input nodes and a second source of voltage level different in voltage level from said first source of voltage level, each of said first and second load means being smaller in conductance than said memory cell.
Claim 3
Dependent Claim
104 words
A sense amplifier circuit as set forth in claim 1, in which said memory cell has a memory transistor coupled between said signal line and said second source of voltage level for a true data bit and another memory transistor coupled between said complementary signal line and said second source of voltage level for a complementary data bit of said true data bit, and in which each of said first and second load means is implemented by a series combination of load transistors identical in transistor type with said memory transistors and coupled between said input node and said second source of voltage level.
Claim 4
Dependent Claim
28 words
A sense amplifier circuit as set forth in claim 2, in which said memory transistors and said load transistors are of a floating avalanche metal oxide semiconductor transistor.
Claim 5
Dependent Claim
152 words
A sense amplifier circuit as set forth in claim 3, in which said output circuit comprises f-1) a series combination of a fifth transistor of said one channel conductivity type, an output node and a sixth transistor of said opposite channel conductivity type coupled between said first and second sources of voltage level, a gate electrode of said fifth transistor being coupled to a gate electrode and a drain node of said first transistor, and f-2) a series combination of a seventh transistor of said one channel conductivity type and an eighth transistor of said opposite channel conductivity type coupled between said first and second sources of voltage level, a gate electrode of said seventh transistor being coupled to a gate electrode and a drain node of said third transistor, a gate electrode of said eighth transistor being coupled to a drain node thereof and a gate electrode of said sixth transistor.
Claim 6
Dependent Claim
39 words
A sense amplifier circuit as set forth in claim 4, in which each of said first and second feedback loops has an inverter circuit coupled between the associated input node and a gate of said second or fourth transistor.
Claim 7
Dependent Claim
80 words
A sense amplifier circuit as set forth in claim 1, in which said memory cell has a memory transistor coupled between said signal line and said second source of voltage level for a true data bit and another memory transistor coupled between said complementary signal line and said second source of voltage level for a complementary data bit of said true data bit, and in which each of said first and second load means is implemented by a resistive element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |