Memory data protection for a ferroelectric memory

Claim 2

A memory device comprising: a power supply for supplying power to said ferroelectric memory device; a memory cell array comprising a plurality of memory cells, each said memory cell comprising a switching transistor and a ferroelectric capacitor, said ferroelectric capacitor being connected to a data line at an electrode thereof through said switching transistor and being connected to a cell electrode line at another electrode thereof, said switching transistor being further connected to a selection line at a control electrode thereof, said switching transistor being forced into conduction when a selection signal appears on said selection line and being forced out of conduction when a non-selection signal appears on said selection line; voltage generating means for generating a first predetermined voltage on said cell electrode line; detecting means for detecting an voltage of said power supply to generate a low-voltage detection signal when said voltage of said power supply is lower than a predetermined threshold voltage; and protective control means responsive to said low-voltage detection signal for fixing said selection line at a second predetermined voltage so as to protect said ferroelectric capacitor from a voltage change of said selection line.

Claim 3

The memory device according to claim 1, wherein said protective control means comprises: a selection line controller for outputting one of said selection signal and said non-selection signal to said selection line according to an address signal received from outside; and protective means responsive to said low-voltage detection signal, for outputting said non-selection signal to said selection line regardless of said address signal.

Claim 4

The memory device according to claim 2, wherein said protective means comprises: a second switching transistor having a first main electrode connected to said selection line and a second main electrode connected to a voltage level of said non-selection signal, said low-voltage detection signal being applied to a third electrode for on and off control of said second switching transistor.

Claim 5

The memory device according to claim 2, wherein said protective means comprises: a first gate circuit for performing a logical NAND function on an output of said selection line controller and said low-voltage detection signal; and a second gate circuit for performing a logical inverse function on an output of said first gate circuit, said low-voltage detection signal lowering an output of said second gate circuit to a voltage level of said non-selection signal.

Claim 6

The memory device according to claim 1, wherein said protective control means comprises: an address buffer for storing an address signal received from outside; a decoder for decoding said address signal to output one of said selection signal and said non-selection signal to said selection line according to said address signal; and a controller responsive to said low-voltage detection signal, for controlling said decoder so as to output said non-selection signal to said selection line regardless of said address signal.

Claim 7

The memory device according to claim 5, wherein said decoder comprises: a first gate circuit for performing a logical NAND function on a decoded signal of said decoder and a control signal received from said controller; and a second gate circuit for performing a logical inverse function on an output of said first gate circuit, said control signal lowering an output of said second gate circuit to a voltage level of said non-selection signal.

Claim 8

The memory device according to claim 1, wherein said second predetermined voltage has a grounding voltage level.

Claim 9

The memory device according to claim 2, wherein said non-selection signal has a grounding voltage level.

Claim 10

The memory device according to claim 3, wherein said non-selection signal has a grounding voltage level.

Claim 11

The memory device according to claim 4, wherein said non-selection signal has a grounding voltage level.

Claim 12

The memory device according to claim 5, wherein said non-selection signal has a grounding voltage level.

Claim 13

The memory device according to claim 6, wherein said non-selection signal has a grounding voltage level.

Claim 14

A memory device comprising: a power supply for supplying power to said ferroelectric memory device; a memory cell array comprising a plurality of memory cells, each said memory cell comprising a switching transistor and a ferroelectric capacitor, said ferroelectric capacitor being connected to a data line at an electrode thereof through said switching transistor and being connected to a cell electrode line at another electrode thereof, said switching transistor being further connected to a selection line at a control electrode thereof, said switching transistor being forced into conduction when a selection signal appears on said selection line and being forced out of conduction when a non-selection signal appears on said selection line; voltage generating means for generating a first predetermined voltage on said cell electrode line; detecting means for detecting a voltage of said power supply to generate a low-voltage detection signal when said voltage of said power supply is lower than a predetermined threshold voltage; and protective control means responsive to said low-voltage detection signal for fixing said data line at a second predetermined voltage so as to protect said ferroelectric capacitor from a voltage change of said selection line.

Claim 15

A memory device comprising: a power supply for supplying power to said ferroelectric memory device; a memory cell array comprising a plurality of memory cells, each said memory cell comprising a switching transistor and a ferroelectric capacitor, said ferroelectric capacitor being connected to a data line at an electrode thereof through said switching transistor and being connected to a cell electrode line at another electrode thereof, said switching transistor being further connected to a selection line at a control electrode thereof, said switching transistor being forced into conduction when a selection signal appears on said selection line and being forced out of conduction when a non-selection signal appears on said selection line; voltage generating means for generating a first predetermined voltage on said cell electrode line; detecting means for detecting a voltage of said power supply to generate a low-voltage detection signal when said voltage of said power supply is lower than a predetermined threshold voltage; and protective control means responsive to said low-voltage detection signal for fixing said data line at a second predetermined voltage so as to protect said ferroelectric capacitor from a voltage change of said selection line.

Claim 16

The memory device according to claim 13, wherein said protective control means comprises: a voltage equalizing means responsive to said low-voltage detection signal, for equalizing a voltage level of said data line to said second predetermined voltage.

Claim 17

The memory device according to claim 14, wherein said second predetermined voltage is equal to said first predetermined voltage.

Claim 18

A memory device comprising: a power supply for supplying power to said memory device; a memory cell array comprising a plurality of memory cells arranged in a first number of rows and a second number of columns, memory cells of each said column being connected in common to a word line, memory cells of each said row being connected alternately to one of a pair of data lines, each said memory cell comprising a switching transistor and a ferroelectric capacitor, said ferroelectric capacitor being connected to said data line at an electrode thereof through said switching transistor and being connected to a plate line at another electrode thereof, said switching transistor being connected to said word line at a control electrode thereof, said switching transistor being forced into conduction when a selection signal appears on said word line and being forced out of conduction when a non-selection signal appears on said word line; said first number of sense amplifiers each connected to said pair of data lines; a voltage generating circuit for generating a first predetermined voltage on said plate line; a voltage detector for detecting a voltage of said power supply to generate a low-voltage detection signal when said voltage of said power supply is lower than a predetermined threshold voltage; a word-line controller for outputting one of said selection signal and said non-selection signal to said word line according to an address signal received from outside; and a protective circuit responsive to said low-voltage detection signal for outputting said non-selection signal to said word line regardless of said address signal.

Claim 19

A memory device comprising: a power supply for supplying power to said memory device; a memory cell array comprising a plurality of memory cells arranged in a first number of rows and a second number of columns, memory cells of each said column being connected in common to a word line, memory cells of each said row being connected alternately to one of a pair of data lines, each said memory cell comprising a switching transistor and a ferroelectric capacitor, said ferroelectric capacitor being connected to said data line at an electrode thereof through said switching transistor and being connected to a plate line at another electrode thereof, said switching transistor being connected to said word line at a control electrode thereof, said switching transistor being forced into conduction when a selection signal appears on said word line and being forced out of conduction when a non-selection signal appears on said word line; said first number of sense amplifiers each connected to said pair of data lines; a voltage generating circuit for generating a first predetermined voltage on said plate line; a voltage detector for detecting a voltage of said power supply to generate a low-voltage detection signal when said voltage of said power supply is lower than a predetermined threshold voltage; a word-line controller for outputting one of said selection signal and said non-selection signal to said word line according to an address signal received from outside; and a protective circuit responsive to said low-voltage detection signal for outputting said non-selection signal to said word line regardless of said address signal.

Claim 20

The memory device according to claim 16, wherein said non-selection signal has a grounding voltage level.

Claim 21

A memory device comprising: a power supply for supplying power to said memory device; a memory cell array comprising a plurality of memory cells arranged in a first number of rows and a second number of columns, memory cells of each said column being connected in common to a word line, memory cells of each said row being connected alternately to one of a pair of data lines, each said memory cell comprising a switching transistor and a ferroelectric capacitor, said ferroelectric capacitor being connected to said data line at an electrode thereof through said switching transistor and being connected to a plate line at another electrode thereof, said switching transistor being connected to said word line at a control electrode thereof, said switching transistor being forced into conduction when a selection signal appears on said word line and being forced out of conduction when a non-selection signal appears on said word line; said first number of sense amplifiers each connected to said pair of data lines; a voltage generating circuit for generating a first predetermined voltage on said plate line; a voltage detector for detecting a voltage of said power supply to generate a low-voltage detection signal when said voltage of said power supply is lower than a predetermined threshold voltage; a word-line controller for outputting one of said selection signal and said non-selection signal to said word line according to an address signal received from outside; and a voltage equalizing circuit responsive to said low-voltage detection signal, for equalizing a voltage level of said data line to said first predetermined voltage.

Claim 22

A memory device comprising: a power supply for supplying power to said memory device; a memory cell array comprising a plurality of memory cells arranged in a first number of rows and a second number of columns, memory cells of each said column being connected in common to a word line, memory cells of each said row being connected alternately to one of a pair of data lines, each said memory cell comprising a switching transistor and a ferroelectric capacitor, said ferroelectric capacitor being connected to said data line at an electrode thereof through said switching transistor and being connected to a plate line at another electrode thereof, said switching transistor being connected to said word line at a control electrode thereof, said switching transistor being forced into conduction when a selection signal appears on said word line and being forced out of conduction when a non-selection signal appears on said word line; said first number of sense amplifiers each connected to said pair of data lines; a voltage generating circuit for generating a first predetermined voltage on said plate line; a voltage detector for detecting a voltage of said power supply to generate a low-voltage detection signal when said voltage of said power supply is lower than a predetermined threshold voltage; a word-line controller for outputting one of said selection signal and said non-selection signal to said word line according to an address signal received from outside; and a voltage equalizing circuit responsive to said low-voltage detection signal, for equalizing a voltage level of said data line to said first predetermined voltage.