Semiconductor memory device with provision of pseudo-acceleration test

Claim 2

A semiconductor memory device comprising: a memory cell array including memory cells; means, connected to said memory cell array, for selecting one of said memory cells; means, connected to said memory cell array, for reading and outputting data from a memory cell selected by said selecting means; means, connected to said selecting means, for receiving an activation signal and a pseudo-acceleration test signal to generate a driving signal for driving said selecting means, said driving signal being generated by delaying said activation signal with a definite delay time period which is changed in response to said pseudo-acceleration test signal; means, connected to said driving signal generating means and said reading and outputting means, for determining whether said driving signal generating means is normal or abnormal, to transmit a determination signal to said reading and outputting means.

Claim 3

A device as set forth in claim 1, wherein said determining means brings said reading and outputting means to a high impedance state when said driving signal generating means is abnormal.

Claim 4

A device as set forth in claim 1, wherein said determining means determines whether or not said driving signal is received when receiving said activation signal, to thereby determine that said driving signal generating means is abnormal when said driving signal is not received.

Claim 5

A semiconductor memory device comprising: a memory cell array including memory cells in rows and columns; a row selecting means, connected to said memory cell array, for selecting one row of said memory cells; a column selecting means, connected to said memory cell array, for selecting one column of said memory cells; an outputting means, connected to said memory cell array, for outputting data from a memory cell selected by said row selecting means and said column selecting means; a driving means, connected to said row selecting means, for receiving an activation signal and a pseudo-acceleration test signal to generate a driving signal for driving said row selecting means, said driving signal being generated by delaying said activation signal with a definite delay time period which is changed in response to said pseudo-acceleration test signal; a determining means, connected to said driving means and said outputting means, for determining whether said driving means is normal or abnormal, to transmit a determination signal to said outputting means.

Claim 6

A semiconductor memory device comprising: a memory cell array including memory cells in rows and columns; a row selecting means, connected to said memory cell array, for selecting one row of said memory cells; a column selecting means, connected to said memory cell array, for selecting one column of said memory cells; an outputting means, connected to said memory cell array, for outputting data from a memory cell selected by said row selecting means and said column selecting means; a driving means, connected to said row selecting means, for receiving an activation signal and a pseudo-acceleration test signal to generate a driving signal for driving said row selecting means, said driving signal being generated by delaying said activation signal with a definite delay time period which is changed in response to said pseudo-acceleration test signal; a determining means, connected to said driving means and said outputting means, for determining whether said driving means is normal or abnormal, to transmit a determination signal to said outputting means.

Claim 7

A device as set forth in claim 4, wherein said determining means brings said outputting means to a high impedance state when said driving means is abnormal.

Claim 8

A device as set forth in claim 4, wherein said determining means determines whether or not said driving signal is received when said activation signal is received, to thereby determine that said driving means is abnormal when said driving signal is not received.

Claim 9

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a memory cell array including memory cells connected to said word lines and said bit lines; a word line selecting means, connected to said word lines, for selecting one of said word lines; a bit line selecting means, connected to said bit lines, for selecting one of said bit lines, an output buffer, connected to said memory cell array, for outputting data from a memory cell selected by said word line selecting means and said bit line selecting means; a word line driving circuit, connected to said word line selecting means, for receiving an activation signal and a pseudo-acceleration test signal to generate a driving signal for driving said word line selecting means, said driving signal being generated by delaying said activation signal with a definite delay time period which is changed in response to said pseudo-acceleration test signal; and a word line driving circuit determining circuit, connected to said word line driving circuit and said output buffer, for determining whether said word line driving circuit is normal or abnormal, to transmit a determination signal to said output buffer.

Claim 10

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a memory cell array including memory cells connected to said word lines and said bit lines; a word line selecting means, connected to said word lines, for selecting one of said word lines; a bit line selecting means, connected to said bit lines, for selecting one of said bit lines, an output buffer, connected to said memory cell array, for outputting data from a memory cell selected by said word line selecting means and said bit line selecting means; a word line driving circuit, connected to said word line selecting means, for receiving an activation signal and a pseudo-acceleration test signal to generate a driving signal for driving said word line selecting means, said driving signal being generated by delaying said activation signal with a definite delay time period which is changed in response to said pseudo-acceleration test signal; and a word line driving circuit determining circuit, connected to said word line driving circuit and said output buffer, for determining whether said word line driving circuit is normal or abnormal, to transmit a determination signal to said output buffer.

Claim 11

A device as set forth in claim 7, wherein said word line driving circuit determining circuit brings said output buffer to a high impedance state when said word line driving circuit is abnormal.

Claim 12

A device as set forth in claim 7, wherein said word line driving circuit determining circuit determines whether or not said driving signal is received when said activation signal is received, to thereby determine that said word line driving circuit is abnormal when said driving signal is not received.

Claim 13

A device as set forth in claim 7, wherein said word line selecting means comprises: a row address buffer for generating row address signals and their inverted signals; a row address decoder, connected to said row address buffer, for receiving said row address signals and their inverted signals to generate a row selection signal; and a row selecting circuit, connected to said row address decoder and said word line driving circuit, for receiving said row selection signal and said driving signal to drive one of said word lines.

Claim 14

A device as set forth in claim 7, wherein said bit line selecting means comprises: a column address buffer for generating column address signals and their inverted signals; and a column address decoder, connected to said column address buffer, for receiving said column address signals and their inverted signals to drive one of said bit lines.

Claim 15

A device as set forth in claim 7, wherein said word line driving circuit comprises: first and second delay circuits for receiving said activation signal, a delay time period of said first delay circuit being different from that of said second delay circuit; first and second switching circuits connected between a high voltage supply means and a low voltage supply means, said first and second switching circuits being selectively turned ON and OFF in response to one of the outputs of said first and second delay circuits; and a third switching circuit, connected to said first and second delay circuits, for selecting one of said first and second delay circuits in response to said pseudo-acceleration test signal.

Claim 16

A device as set forth in claim 12, wherein said word line driving circuit further comprises a fourth switching circuit in parallel to said first switching circuit, said fourth switching circuit being turned ON and OFF in response to said pseudo-acceleration test signal.

Claim 17

A device as set forth in claim 7, wherein said word line driving circuit determining circuit comprises: a delay circuit for receiving said activation signal; a NOR circuit having an input connected to an output of said delay circuit and another input for receiving said driving signal; a NAND circuit having an input for receiving said activation signal and another input connected to an output of said NOR circuit; and an inverter connected to an output of said NAND circuit.

Claim 18

A device as set forth in claim 7, wherein said output buffer comprises: a first circuit for receiving an output buffer driving signal and said determination signal; a second NOR circuit having an input connected to said OR circuit and another input for receiving said data from said memory cells; a third NOR circuit having an input connected to said OR circuit and another input for receiving inverted data of said data from said memory cells; first and second switching circuits connected between a high voltage supply means and a low voltage supply means, said first switching circuit being turned ON and OFF by an output of said second NOR circuit, said second switching circuit being turned ON and OFF by an output of said third NOR circuit.

Claim 19

A device as set forth in claim 7, wherein said memory cells are of a dynamic type.

Claim 20

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit line pairs; a memory cell array including memory cells connected to said word lines and said bit line pairs; a word line selecting means, connected to said word lines, for selecting one of said word lines; a bit line selecting means, connected to said bit line pairs, for selecting one of said bit line pairs, an output buffer, connected to said memory cell array, for outputting data from a memory cell selected by said word line selecting means and said bit line selecting means; a word line driving circuit, connected to said word line selecting means, for receiving an activation signal and a pseudo-acceleration test signal to generate a driving signal for driving said word line selecting means, said driving signal being generated by delaying said activation signal with a definite delay time period which is changed in response to said pseudo-acceleration test signal; and a word line driving circuit determining circuit, connected to said word line driving circuit and said output buffer, for determining whether said word line driving circuit is normal or abnormal, to transmit a determination signal to said output buffer.

Claim 21

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit line pairs; a memory cell array including memory cells connected to said word lines and said bit line pairs; a word line selecting means, connected to said word lines, for selecting one of said word lines; a bit line selecting means, connected to said bit line pairs, for selecting one of said bit line pairs, an output buffer, connected to said memory cell array, for outputting data from a memory cell selected by said word line selecting means and said bit line selecting means; a word line driving circuit, connected to said word line selecting means, for receiving an activation signal and a pseudo-acceleration test signal to generate a driving signal for driving said word line selecting means, said driving signal being generated by delaying said activation signal with a definite delay time period which is changed in response to said pseudo-acceleration test signal; and a word line driving circuit determining circuit, connected to said word line driving circuit and said output buffer, for determining whether said word line driving circuit is normal or abnormal, to transmit a determination signal to said output buffer.

Claim 22

A device as set forth in claim 17, wherein said word line driving circuit determining circuit brings said output buffer to a high impedance state when said word line driving circuit is abnormal.

Claim 23

A device as set forth in claim 17, wherein said word line driving circuit determining circuit determines whether or not said driving signal is received when said activation signal is received, to thereby determine that said word line driving circuit is abnormal when said driving signal is not received.

Claim 24

A device as set forth in claim 17, wherein said word line selecting means comprises: a row address buffer for generating row address signals and their inverted signals; a row address decoder, connected to said row address buffer, for receiving said row address signals and their inverted signals to generate a row selection signal; and a row selecting circuit, connected to said row address decoder and said word line driving circuit, for receiving said row selection signal and said driving signal to drive one of said word lines.

Claim 25

A device as set forth in claim 17, wherein said bit line selecting means comprises: a column address buffer for generating column address signals and their inverted signals; and a column address decoder, connected to said column address buffer, for receiving said column address signals and their inverted signals to drive one of said bit line pairs.

Claim 26

A device as set forth in claim 17, wherein said word line driving circuit comprises: first and second delay circuits for receiving said activation signal, a delay time period of said first delay circuit being different from that of said second delay circuit; first and second switching circuits connected between a high voltage supply means and a low voltage supply means, said first and second switching circuits being selectively turned ON and OFF in response to one of the outputs of said first and second delay circuits; and a third switching circuit, connected to said first and second delay circuits, for selecting one of said first and second delay circuits in response to said pseudo-acceleration test signal.

Claim 27

A device as set forth in claim 22, wherein said word line driving circuit further comprises a fourth switching circuit in parallel to said first switching circuit, said fourth switching circuit being turned ON and OFF in response to said pseudo-acceleration test signal.

Claim 28

A device as set forth in claim 17, wherein said word line driving circuit determining circuit comprises: a delay circuit for receiving said activation signal; a NOR circuit having an input connected to an output of said delay circuit and another input for receiving said driving signal; a NAND circuit having an input for receiving said activation signal and another input connected to an output of said NOR circuit; and an inverter connected to an output of said NAND circuit.

Claim 29

A device as set forth in claim 17, wherein said output buffer comprises: a first circuit for receiving an output buffer driving signal and said determination signal; a second NOR circuit having an input connected to said OR circuit and another input for receiving said data from said memory cells; a third NOR circuit having an input connected to said OR circuit and another input for receiving inverted data of said data from said memory cells; first and second switching circuits connected between a high voltage supply means and a low voltage supply means, said first switching circuit being turned ON and OFF by an output of said second NOR circuit, said second switching circuit being turned ON and OFF by an output of said third NOR circuit.

Claim 30

A device as set forth in claim 17, wherein said memory cells are of a static type.