Patent US4551519A successfully refreshed from Google Patents.
Patent US5752081A successfully refreshed from Google Patents.
US5752081A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signalling system and method for allowing a direct memory access (DMA) input/output (I/O) device on the peripheral component interconnect (PCI) bus to perform DMA transfers
Assignee: Philips Semiconductors Inc
•
Filing: 1995-06-08
•
Granted: 1998-05-12
•
Expires: 2015-06-08
Abstract
Abstract The present invention relates to an apparatus and method for supporting DMA I/O devices on a PCI bus. A DMA I/O device is coupled to a DMA controller via a serial link and two signal lines. The serial link is used by the DMA I/O device to request a DMA transfer. When the DMA controller receives the serialized DMA request, it sends a signal to an arbiter and waits for the PCI bus to be granted to the DMA controller for use during the DMA transfer. When granted the PCI bus, the DMA controller signals the DMA I/O device. The DMA I/O device asserts a signal in response to the one asserted by the DMA controller. The DMA controller recognizes the signal asserted by the DMA I/O device and continues with the DMA transfer. The transfer continues for as long as the DMA I/O device continues to assert the signal or for as long as the DMA controller is programmed.
Inventors
- 👤 James J. Jirgal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:08
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
364 words
A system for supporting direct memory access (DMA) input/output (I/O) devices on a peripheral component interconnect (PCI) bus comprising, in combination: a PCI bus for transferring data to and from memory; at least one DMA I/O device means directly coupled to said PCI bus for requesting a DMA transfer to at least one of receive data transferred from said memory and to transfer data to said memory; DMA controller means coupled to said PCI bus and directly coupled to said at least one DMA I/O device means for receiving a signal from said at least one DMA I/O device means that a DMA transfer is required and for permitting transfer of said data to said at least one DMA I/O device means from said memory and for permitting transfer of said data from said at least one DMA I/O device means to said memory; serial link signal means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that a DMA transfer is required; arbiter means coupled to said DMA controller means for receiving a signal from said DMA controller means that said DMA transfer has been requested and for granting said PCI bus means to said DMA controller means for said DMA transfer; first signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said at least one DMA I/O device means when said DMA transfer has been granted and for signaling said at least one DMA I/O device means a code indicating active DMA channels as a subset of PCI address lines; second signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said DMA controller means when said at least one DMA I/O device means acknowledges said DMA transfer has been granted, said second signal line means being a realtime representation of said at least one DMA I/O device DMA request and is asserted until said at least one DMA I/O device means requires no more DMA cycles.
Claim 2
Independent Claim
364 words
A system for supporting direct memory access (DMA) input/output (I/O) devices on a peripheral component interconnect (PCI) bus comprising, in combination: a PCI bus for transferring data to and from memory; at least one DMA I/O device means directly coupled to said PCI bus for requesting a DMA transfer to at least one of receive data transferred from said memory and to transfer data to said memory; DMA controller means coupled to said PCI bus and directly coupled to said at least one DMA I/O device means for receiving a signal from said at least one DMA I/O device means that a DMA transfer is required and for permitting transfer of said data to said at least one DMA I/O device means from said memory and for permitting transfer of said data from said at least one DMA I/O device means to said memory; serial link signal means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that a DMA transfer is required; arbiter means coupled to said DMA controller means for receiving a signal from said DMA controller means that said DMA transfer has been requested and for granting said PCI bus means to said DMA controller means for said DMA transfer; first signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said at least one DMA I/O device means when said DMA transfer has been granted and for signaling said at least one DMA I/O device means a code indicating active DMA channels as a subset of PCI address lines; second signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said DMA controller means when said at least one DMA I/O device means acknowledges said DMA transfer has been granted, said second signal line means being a realtime representation of said at least one DMA I/O device DMA request and is asserted until said at least one DMA I/O device means requires no more DMA cycles.
Claim 3
Dependent Claim
28 words
A system for supporting DMA I/O devices on a PCI bus in accordance with claim 1 wherein said DMA controller means is an AT compatible DMA controller means.
Claim 4
Dependent Claim
289 words
A system for supporting DMA I/O devices on a PCI bus in accordance with claim 2 further comprising: secondary PCI bus means coupled to said DMA controller means for carrying said memory data and said data during a DMA transfer over said secondary PCI bus means; at least one secondary DMA I/O device means coupled to said secondary PCI bus means for receiving said memory data transferred from said memory to said at least one secondary DMA I/O device means and for transferring said data to said memory from said at least one secondary DMA I/O device means; serial link signal line means coupled to said at least one secondary DMA I/O device means and said DMA controller means for allowing said at least one secondary DMA I/O device means to signal said DMA controller means that said DMA transfer is required; first signal line means coupled to said at least one secondary DMA I/O device means and to said DMA controller means for signaling said at least one secondary DMA I/O device means when said DMA transfer has been granted and for signaling said at least one secondary DMA I/O device means a code indicating active DMA channels as a subset of PCI address lines; and second signal line means coupled to said at least one secondary DMA I/O device means and to said DMA controller means for signaling said DMA controller means when said at least one secondary DMA I/O device means acknowledges said DMA transfer has been granted, said second signal line means being a realtime representation of said at least one secondary DMA I/O device DMA request and is asserted until said at least one secondary DMA I/O device means requires no more DMA cycles.
Claim 5
Dependent Claim
40 words
A system for supporting DMA I/O devices on a PCI bus in accordance with claim 3 wherein said signaling means coupled to said at least one secondary DMA I/O device means and said DMA controller means is a serial link.
Claim 6
Dependent Claim
46 words
A system for supporting DMA I/O devices on a PCI bus in accordance with claim 4 wherein said arbiter means grants control of said secondary PCI bus means to said DMA controller means when said DMA transfer by said secondary DMA I/O device means is required.
Claim 7
Independent Claim
492 words
A method of transferring memory data from memory to a direct memory (DMA) input/output (I/O) device coupled to a peripheral component interconnect (PCI) bus comprising the steps of: providing a system to support said DMA I/O devices on a PCI bus comprising: at least one DMA I/O device means for receiving said memory data transferred from memory to said at least one DMA I/O device means; DMA controller means coupled to said at least one DMA I/O device means for receiving a signal from said at least one DMA I/O device means that a DMA transfer is required and for permitting transfer of said memory data to said at least one DMA I/O device means from said memory; signaling means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that said DMA transfer is required; arbiter means coupled to said DMA controller means for receiving a signal from said DMA controller means that said DMA transfer has been requested and for granting said PCI bus means to said DMA controller means for said DMA transfer; first signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said at least one DMA I/O device means when said DMA transfer has been granted; second signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said DMA controller means when said at least one DMA I/O device means acknowledges said DMA transfer has been granted; and PCI bus means coupled to said at least one DMA I/O device means for transferring said memory data to said at least one DMA I/O device means from said memory; sending a signal from said DMA I/O device means to said DMA controller means via said serial link means coupled to said DMA I/O device means and said DMA controller means requesting said DMA transfer from said memory to said DMA I/O device means; sending a signal from said DMA controller means to said arbiter means when said DMA controller means receives said signal that said DMA transfer from said memory to said DMA I/O device means is required; waiting for said arbiter means to grant said PCI bus means to said DMA controller means for use during said DMA transfer; sending a signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; sending a signal from said DMA I/O device means to said DMA controller means acknowledging said signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; and transferring said memory data from said memory to said DMA I/O device means.
Claim 8
Independent Claim
492 words
A method of transferring memory data from memory to a direct memory (DMA) input/output (I/O) device coupled to a peripheral component interconnect (PCI) bus comprising the steps of: providing a system to support said DMA I/O devices on a PCI bus comprising: at least one DMA I/O device means for receiving said memory data transferred from memory to said at least one DMA I/O device means; DMA controller means coupled to said at least one DMA I/O device means for receiving a signal from said at least one DMA I/O device means that a DMA transfer is required and for permitting transfer of said memory data to said at least one DMA I/O device means from said memory; signaling means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that said DMA transfer is required; arbiter means coupled to said DMA controller means for receiving a signal from said DMA controller means that said DMA transfer has been requested and for granting said PCI bus means to said DMA controller means for said DMA transfer; first signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said at least one DMA I/O device means when said DMA transfer has been granted; second signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said DMA controller means when said at least one DMA I/O device means acknowledges said DMA transfer has been granted; and PCI bus means coupled to said at least one DMA I/O device means for transferring said memory data to said at least one DMA I/O device means from said memory; sending a signal from said DMA I/O device means to said DMA controller means via said serial link means coupled to said DMA I/O device means and said DMA controller means requesting said DMA transfer from said memory to said DMA I/O device means; sending a signal from said DMA controller means to said arbiter means when said DMA controller means receives said signal that said DMA transfer from said memory to said DMA I/O device means is required; waiting for said arbiter means to grant said PCI bus means to said DMA controller means for use during said DMA transfer; sending a signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; sending a signal from said DMA I/O device means to said DMA controller means acknowledging said signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; and transferring said memory data from said memory to said DMA I/O device means.
Claim 9
Dependent Claim
72 words
The method of claim 6 wherein said step of providing a system to support said DMA I/O devices on a PCI bus further comprises the step of providing serial link means for said signaling means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that said DMA transfer is required.
Claim 10
Dependent Claim
57 words
The method of claim 7 wherein said step of sending a signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted further comprising the step of presenting a code indicating active DMA channels on a subset of said PCI bus means.
Claim 11
Dependent Claim
52 words
The method of claim 8 wherein said step of transferring said memory data from said memory to said DMA I/O device means comprises the steps of: reading said memory data from said memory to a temporary location; and writing said memory data from said temporary location to said DMA I/O device means.
Claim 12
Dependent Claim
14 words
The method of claim 9 wherein said temporary location is said DMA controller means.
Claim 13
Independent Claim
485 words
A method of transferring data from a direct memory access (DMA) input/output (I/O) device coupled to a peripheral component interconnect (PCI) bus to memory comprising the steps of: providing a system to support DMA I/O devices on a PCI bus comprising: at least one DMA I/O device means for transferring said data to said memory from said at least one DMA I/O device means; DMA controller means coupled to said at least one DMA I/O device means for receiving a signal from said at least one DMA I/O device means that a DMA transfer is required and for permitting transfer of said data from said at least one DMA I/O device means to said memory; signaling means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that a DMA transfer is required; arbiter means coupled to said DMA controller means for receiving a signal from said DMA controller means that said DMA transfer has been requested and for granting said PCI bus means to said DMA controller means for said DMA transfer; first signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said at least one DMA I/O device means when said DMA transfer has been granted; second signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said DMA controller means when said at least one DMA I/O device means acknowledges said DMA transfer has been granted; and PCI bus means coupled to said at least one DMA I/O device means for transferring said data from said at least one DMA I/O device means to said memory; sending a signal from said DMA I/O device means to said DMA controller means via said serial link means between said DMA I/O device and said DMA controller means requesting said DMA transfer to said memory from said DMA I/O device means; sending a signal from said DMA controller means to said arbiter means when said DMA controller means receives said signal that said DMA transfer to said memory from said DMA I/O device means is required; waiting for said arbiter means to grant said PCI bus means to said DMA controller means for use during said DMA transfer; sending a signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; sending a signal from said DMA I/O device means to said DMA controller means acknowledging said signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; and transferring said data from said DMA I/O device means to said memory.
Claim 14
Independent Claim
485 words
A method of transferring data from a direct memory access (DMA) input/output (I/O) device coupled to a peripheral component interconnect (PCI) bus to memory comprising the steps of: providing a system to support DMA I/O devices on a PCI bus comprising: at least one DMA I/O device means for transferring said data to said memory from said at least one DMA I/O device means; DMA controller means coupled to said at least one DMA I/O device means for receiving a signal from said at least one DMA I/O device means that a DMA transfer is required and for permitting transfer of said data from said at least one DMA I/O device means to said memory; signaling means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that a DMA transfer is required; arbiter means coupled to said DMA controller means for receiving a signal from said DMA controller means that said DMA transfer has been requested and for granting said PCI bus means to said DMA controller means for said DMA transfer; first signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said at least one DMA I/O device means when said DMA transfer has been granted; second signal line means coupled to said at least one DMA I/O device means and to said DMA controller means for signaling said DMA controller means when said at least one DMA I/O device means acknowledges said DMA transfer has been granted; and PCI bus means coupled to said at least one DMA I/O device means for transferring said data from said at least one DMA I/O device means to said memory; sending a signal from said DMA I/O device means to said DMA controller means via said serial link means between said DMA I/O device and said DMA controller means requesting said DMA transfer to said memory from said DMA I/O device means; sending a signal from said DMA controller means to said arbiter means when said DMA controller means receives said signal that said DMA transfer to said memory from said DMA I/O device means is required; waiting for said arbiter means to grant said PCI bus means to said DMA controller means for use during said DMA transfer; sending a signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; sending a signal from said DMA I/O device means to said DMA controller means acknowledging said signal from said DMA controller means to said DMA I/O device means that use of said PCI bus means for said DMA transfer has been granted; and transferring said data from said DMA I/O device means to said memory.
Claim 15
Dependent Claim
72 words
The method of claim 10 wherein said step of providing a system to support said DMA I/O devices on a PCI bus further comprises the step of providing serial link means for said signaling means coupled to said at least one DMA I/O device means and said DMA controller means for allowing said at least one DMA I/O device means to signal said DMA controller means that said DMA transfer is required.
Claim 16
Dependent Claim
57 words
The method of claim 12 wherein said step of sending a signal from said DMA I/O device means to said DMA controller means that use of said PCI bus means for said DMA transfer has been granted further comprising the step of presenting a code indicating active DMA channels on a subset of said PCI bus means.
Claim 17
Dependent Claim
49 words
The method of claim 13 wherein said step of transferring said data from said DMA I/O device means to said memory comprises the steps of: reading said data from said DMA I/O device means to a temporary location; and writing said data from said temporary location to said memory.
Claim 18
Dependent Claim
14 words
The method of claim 14 wherein said temporary location is said DMA controller means.
References Cited (Backward Citations)
US4099236A
Cited
US4490788A
Cited
US4729090A
Cited
US5438666A
Cited
US5212795A
Cited
US5442753A
Cited
US5381538A
Cited
US5450551A
Cited
US5655151A
Cited
US5517325A
Cited
US5561820A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |