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US5752045A
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Power conservation in synchronous SRAM cache memory blocks of a computer system
Assignee: United Microelectronics Corp
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Filing: 1995-07-14
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Granted: 1998-05-12
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Expires: 2015-07-14
Abstract
Abstract A synchronous cache memory power conservation apparatus for conserving power of the cache SRAM memory blocks in cached computer systems. The power conservation apparatus is included as a portion of the logic of the cache controller of the computer system. The power conservation apparatus monitors the CPU bus cycles in order to shut off the clocking signals supplied to the cache SRAM memory blocks when the CPU is not accessing the cache memory, thereby reducing the power consumption of the high-power SRAM devices. The power conservation apparatus resumes standard synchronized clocking to the cache SRAM blocks when the CPU is performing a cache-hit memory access cycle for maximum cache access performance.
Inventors
- 👤 David Yu Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:52
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/325; G06F1/3275; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G11; G11C; G11C7/00; G11C7/22; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
259 words
A cache memory power conserving apparatus for controlling a plurality of cache SRAM blocks in a computer system, said computer system including a CPU, a first signal bus, said plurality of cache SRAM blocks coupled to said first signal bus, a cache controller coupled to said plurality of cache SRAM blocks, and a second signal bus coupling said CPU and said cache controller, wherein said CPU and said cache controller are driven by a same CPU clock pulse, and said cache memory power conserving apparatus is included in said cache controller and comprises: synchronization logic coupled to said second signal bus of said CPU to monitor CPU status signals as conveyed on said second signal bus to generate a first selection signal when said CPU is in an idling cycle, and to generate a second selection signal when said CPU is in a cache hit memory access cycle; and a multiplexer having an output coupled to said plurality of cache SRAM blocks and receiving one of said first selection signal and said second selection signal generated by said synchronization logic, wherein said multiplexer multiplexes said same CPU clock pulse to said plurality of cache SRAM blocks when said second selection signal is received from said synchronization logic, allowing for synchronized CPU access to said plurality of cache SRAM blocks, and said multiplexer multiplexes a static signal to said plurality of cache SRAM blocks when said first selection signal is received from said synchronization logic, allowing said plurality of cache SRAM blocks to remain in an idling power conserving mode.
Claim 2
Dependent Claim
259 words
A cache memory power conserving apparatus for controlling a plurality of cache SRAM blocks in a computer system, said computer system including a CPU, a first signal bus, said plurality of cache SRAM blocks coupled to said first signal bus, a cache controller coupled to said plurality of cache SRAM blocks, and a second signal bus coupling said CPU and said cache controller, wherein said CPU and said cache controller are driven by a same CPU clock pulse, and said cache memory power conserving apparatus is included in said cache controller and comprises: synchronization logic coupled to said second signal bus of said CPU to monitor CPU status signals as conveyed on said second signal bus to generate a first selection signal when said CPU is in an idling cycle, and to generate a second selection signal when said CPU is in a cache hit memory access cycle; and a multiplexer having an output coupled to said plurality of cache SRAM blocks and receiving one of said first selection signal and said second selection signal generated by said synchronization logic, wherein said multiplexer multiplexes said same CPU clock pulse to said plurality of cache SRAM blocks when said second selection signal is received from said synchronization logic, allowing for synchronized CPU access to said plurality of cache SRAM blocks, and said multiplexer multiplexes a static signal to said plurality of cache SRAM blocks when said first selection signal is received from said synchronization logic, allowing said plurality of cache SRAM blocks to remain in an idling power conserving mode.
Claim 3
Dependent Claim
20 words
The cache memory power conserving apparatus of claim 1, wherein said plurality of cache SRAM blocks comprise synchronous SRAM devices.
Claim 4
Dependent Claim
45 words
The cache memory power conserving apparatus of claim 2, wherein said cache controller further comprises a comparator for comparing an address issued by said CPU in a memory access cycle, said comparator determining an occurrence of a cache hit condition in said memory access cycle.
Claim 5
Dependent Claim
35 words
The cache memory power conserving apparatus of claim 3, wherein said cache controller further comprises a tag RAM to store a tag address for said address issued by said CPU in said memory access cycle.
Claim 6
Dependent Claim
25 words
The cache memory power conserving apparatus of claim 1, wherein said static signal multiplexed to said plurality of cache SRAM blocks is a ground signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |