US5539681A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuitry and method for reducing power consumption within an electronic circuit
Assignee: International Business Machines Corp
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Filing: 1996-01-04
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Granted: 1996-07-23
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Expires: 2016-01-04
Abstract
Abstract A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.
Inventors
- 👤 Michael C. Alexander
- 👤 Arturo L. Arizpe
- 👤 Gianfranco Gerosa
- 👤 James A. Kahle
- 👤 Aubrey D. Ogden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
152 words
Circuitry, comprising: a bus; an interface unit for performing operations and generating a first signal indicating whether a predefined operation is being performed by said interface unit, said operations including inputting information from said bus and outputting said information in response to a second signal; an input unit for outputting a third signal and inputting said information; a memory coupled to said interface unit and said input unit for outputting said information to said input unit in response to said third signal, wherein if said information is not stored in said memory then, in response to said third signal, said memory further outputs said second signal to said interface unit, inputs said information from said interface unit, and stores said information; and adjusting circuitry coupled to said interface unit and to said memory for adjusting a frequency of clock transitions within said interface unit in response to said first and second signals.
Claim 2
Dependent Claim
152 words
Circuitry, comprising: a bus; an interface unit for performing operations and generating a first signal indicating whether a predefined operation is being performed by said interface unit, said operations including inputting information from said bus and outputting said information in response to a second signal; an input unit for outputting a third signal and inputting said information; a memory coupled to said interface unit and said input unit for outputting said information to said input unit in response to said third signal, wherein if said information is not stored in said memory then, in response to said third signal, said memory further outputs said second signal to said interface unit, inputs said information from said interface unit, and stores said information; and adjusting circuitry coupled to said interface unit and to said memory for adjusting a frequency of clock transitions within said interface unit in response to said first and second signals.
Claim 3
Dependent Claim
18 words
The circuitry of claim 1 wherein said adjusting circuitry increases said frequency in response to said second signal.
Claim 4
Dependent Claim
32 words
The circuitry of claim 2 wherein said adjusting circuitry reduces said frequency in response to said second signal being absent and said first signal indicating said predefined operation is not being performed.
Claim 5
Dependent Claim
17 words
The circuitry of claim 1 wherein said input unit is an instruction buffer/dispatch unit of a processor.
Claim 6
Dependent Claim
12 words
The circuitry of claim 1 wherein said memory is a cache memory.
Claim 7
Dependent Claim
14 words
The circuitry of claim 5 wherein said cache memory is an instruction cache memory.
Claim 8
Dependent Claim
14 words
The circuitry of claim 5 wherein said cache memory is a data cache memory.
Claim 9
Dependent Claim
12 words
The circuitry of claim 1 wherein said bus is a system bus.
Claim 10
Dependent Claim
161 words
Circuitry, comprising: a bus; an interface unit for performing operations and generating a first signal indicating whether a predefined operation is being performed by said interface unit, said operations including inputting information from said bus and outputting said information in response to a second signal; an input unit for outputting a third signal and inputting said information; a memory coupled to said interface unit and said input unit and including first circuitry for outputting said information to said input unit in response to said third signal, wherein if said information is not stored in said memory then, in response to said third signal, said first circuitry further outputs said second signal to said interface unit, inputs said information from said interface unit, and stores said information in said memory; and second circuitry coupled to said first circuitry for adjusting a frequency of clock transitions within at least a subset of said first circuitry in response to said first and second signals.
Claim 11
Dependent Claim
161 words
Circuitry, comprising: a bus; an interface unit for performing operations and generating a first signal indicating whether a predefined operation is being performed by said interface unit, said operations including inputting information from said bus and outputting said information in response to a second signal; an input unit for outputting a third signal and inputting said information; a memory coupled to said interface unit and said input unit and including first circuitry for outputting said information to said input unit in response to said third signal, wherein if said information is not stored in said memory then, in response to said third signal, said first circuitry further outputs said second signal to said interface unit, inputs said information from said interface unit, and stores said information in said memory; and second circuitry coupled to said first circuitry for adjusting a frequency of clock transitions within at least a subset of said first circuitry in response to said first and second signals.
Claim 12
Dependent Claim
25 words
The circuitry of claim 9 wherein said second circuitry increases said frequency in response to said first signal indicating said predefined operation is being performed.
Claim 13
Dependent Claim
30 words
The circuitry of claim 10 wherein said second circuitry reduces said frequency in response to said second signal and said first signal indicating said predefined operation is not being performed.
Claim 14
Dependent Claim
15 words
The circuitry of claim 11 wherein said predefined operation is said operation of outputting information.
Claim 15
Dependent Claim
20 words
The circuitry of claim 12 wherein said operation of outputting information includes an operation of outputting information to said memory.
Claim 16
Dependent Claim
17 words
The circuitry of claim 9 wherein said input unit is an instruction buffer/dispatch unit of a processor.
Claim 17
Dependent Claim
12 words
The circuitry of claim 9 wherein said memory is a cache memory.
Claim 18
Dependent Claim
14 words
The circuitry of claim 15 wherein said cache memory is an instruction cache memory.
Claim 19
Dependent Claim
14 words
The circuitry of claim 15 wherein said cache memory is a data cache memory.
Claim 20
Dependent Claim
12 words
The circuitry of claim 9 wherein said bus is a system bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |