Patent US5748538A successfully refreshed from Google Patents.
US5748538A
Expired / Lapsed
US
⏱️ 0.0 years remaining
OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array
Assignee: Secure Axcess LLC
•
Filing: 1996-11-14
•
Granted: 1998-05-05
•
Expires: 2016-11-14
Abstract
Abstract A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.
Inventors
- 👤 Peter W. Lee
- 👤 Hsing-Ya Tsao
- 👤 Fu-Chang Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:09
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3413; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C11/5642; G11C16/04; G11C16/0491; G11C16/08; G11C16/10; G11C16/14; G11C16/16; G11C16/3409; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C8/00; G11C8/08; G11C8/10; G11C8/12; H; H10; H10B; H10B69/00; G11C16/24; G11C2211/00; G11C2211/56; G11C2211/564; G11C2211/5644; G11C7/00; G11C7/10; G11C7/1006; G11C7/18; G11C8/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
362 words
A memory cell array comprising a matrix of basic circuits, each of said basic circuits including: first and second word lines; first and second source control lines; first and second drain control lines; first, second and third main source lines; first and second main bit lines; two rows and four columns of transistor cells, said transistor cells in each of said rows having gate terminals which are coupled to a respective one of said first and second word lines, said transistor cells in each of said columns having source terminals coupled to a respective one of first, second, third and fourth sub-source lines, and drain terminals coupled to a respective one of first, second, third and fourth sub-bit lines; a first source control gate pair including first source control gates with gate terminals coupled to said first source control line, each of said first source control gates further having a drain terminal coupled to a respective one of said first and fourth sub-source lines, and a source terminal coupled to a respective one of said first and third main source lines; a second source control gate pair including second source control gates with gate terminals coupled to said second source control line, each of said second source control gates further having a drain terminal coupled to a respective one of said second and third sub-source lines, and a source terminal coupled to said second main source line; a first drain control gate pair including first drain control gates with gate terminals coupled to said first drain control line, each of said first drain control gates further having a drain terminal coupled to a respective one of said first and fourth sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines; and a second drain control gate pair including second drain control gates with gate terminals coupled to said second drain control line, each of said second drain control gates further having a drain terminal coupled to a respective one of said second and third sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines.
Claim 2
Dependent Claim
362 words
A memory cell array comprising a matrix of basic circuits, each of said basic circuits including: first and second word lines; first and second source control lines; first and second drain control lines; first, second and third main source lines; first and second main bit lines; two rows and four columns of transistor cells, said transistor cells in each of said rows having gate terminals which are coupled to a respective one of said first and second word lines, said transistor cells in each of said columns having source terminals coupled to a respective one of first, second, third and fourth sub-source lines, and drain terminals coupled to a respective one of first, second, third and fourth sub-bit lines; a first source control gate pair including first source control gates with gate terminals coupled to said first source control line, each of said first source control gates further having a drain terminal coupled to a respective one of said first and fourth sub-source lines, and a source terminal coupled to a respective one of said first and third main source lines; a second source control gate pair including second source control gates with gate terminals coupled to said second source control line, each of said second source control gates further having a drain terminal coupled to a respective one of said second and third sub-source lines, and a source terminal coupled to said second main source line; a first drain control gate pair including first drain control gates with gate terminals coupled to said first drain control line, each of said first drain control gates further having a drain terminal coupled to a respective one of said first and fourth sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines; and a second drain control gate pair including second drain control gates with gate terminals coupled to said second drain control line, each of said second drain control gates further having a drain terminal coupled to a respective one of said second and third sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines.
Claim 3
Dependent Claim
26 words
The memory cell array as claimed in claim 1, wherein each of said sub-bit lines and said sub-source lines is formed as a buried N+ layer.
Claim 4
Dependent Claim
35 words
The memory cell array as claimed in claim 1, wherein each of said sub-bit lines and said sub-source lines is disposed between one of said main source lines and one of said main bit lines.
Claim 5
Dependent Claim
28 words
The memory cell array as claimed in claim 1, wherein each of said transistor cells, said source control gates and said drain control gates is an N-channel cell.
Claim 6
Dependent Claim
28 words
The memory cell array as claimed in claim 1, wherein each of said transistor cells, said source control gates and said drain control gates is a P-channel cell.
Claim 7
Dependent Claim
368 words
A memory cell array comprising a matrix of basic circuits, each of said basic circuits including: first and second word lines; first and second source control lines; first and second drain control lines; first, second and third main source lines; first and second main bit lines; two rows and four columns of transistor cells, said transistor cells in each of said rows having gate terminals which are coupled to a respective one of said first and second word lines, said transistor cells in each of said columns having source terminals coupled to a respective one of first, second, third and fourth sub-source lines, and drain terminals coupled to a respective one of first, second, third and fourth sub-bit lines; a first source control gate pair including first source control gates with gate terminals coupled to said first source control line, each of said first source control gates further having a drain terminal coupled to a respective one of said first and third sub-source lines, and a source terminal coupled to a respective one of said first and second main source lines; a second source control gate pair including second source control gates with gate terminals coupled to said second source control line, each of said second source control gates further having a drain terminal coupled to a respective one of said second and fourth sub-source lines, and a source terminal coupled to a respective one of said first and second main bit lines; a first drain control gate pair including first drain control gates with gate terminals coupled to said first drain control line, each of said first drain control gates further having a drain terminal coupled to a respective one of said first and third sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines; and a second drain control gate pair including second drain control gates with gate terminals coupled to said second drain control line, each of said second drain control gates further having a drain terminal coupled to a respective one of said second and fourth sub-bit lines, and a source terminal coupled to a respective one of said second and third main source lines.
Claim 8
Dependent Claim
368 words
A memory cell array comprising a matrix of basic circuits, each of said basic circuits including: first and second word lines; first and second source control lines; first and second drain control lines; first, second and third main source lines; first and second main bit lines; two rows and four columns of transistor cells, said transistor cells in each of said rows having gate terminals which are coupled to a respective one of said first and second word lines, said transistor cells in each of said columns having source terminals coupled to a respective one of first, second, third and fourth sub-source lines, and drain terminals coupled to a respective one of first, second, third and fourth sub-bit lines; a first source control gate pair including first source control gates with gate terminals coupled to said first source control line, each of said first source control gates further having a drain terminal coupled to a respective one of said first and third sub-source lines, and a source terminal coupled to a respective one of said first and second main source lines; a second source control gate pair including second source control gates with gate terminals coupled to said second source control line, each of said second source control gates further having a drain terminal coupled to a respective one of said second and fourth sub-source lines, and a source terminal coupled to a respective one of said first and second main bit lines; a first drain control gate pair including first drain control gates with gate terminals coupled to said first drain control line, each of said first drain control gates further having a drain terminal coupled to a respective one of said first and third sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines; and a second drain control gate pair including second drain control gates with gate terminals coupled to said second drain control line, each of said second drain control gates further having a drain terminal coupled to a respective one of said second and fourth sub-bit lines, and a source terminal coupled to a respective one of said second and third main source lines.
Claim 9
Dependent Claim
26 words
The memory cell array as claimed in claim 6, wherein each of said sub-bit lines and said sub-source lines is formed as a buried N+ layer.
Claim 10
Dependent Claim
35 words
The memory cell array as claimed in claim 6, wherein each of said sub-bit lines and said sub-source lines is disposed between one of said main source lines and one of said main bit lines.
Claim 11
Dependent Claim
219 words
A memory cell array comprising a matrix of basic circuits, each of said basic circuits including: first and second word lines; first and second drain control lines; first and second main bit lines; two rows and four columns of transistor cells, said transistor cells in each of said rows having gate terminals which are coupled to a respective one of said first and second word lines, said transistor cells in each of said columns having grounded source terminals, and drain terminals coupled to a respective one of first, second, third and fourth sub-bit lines; a first drain control gate pair including first drain control gates with gate terminals coupled to said first drain control line, each of said first drain control gates further having a drain terminal coupled to a respective one of said first and third sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines; and a second drain control gate pair including second drain control gates with gate terminals coupled to said second drain control line, each of said second drain control gates further having a drain terminal coupled to a respective one of said second and fourth sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines.
Claim 12
Dependent Claim
219 words
A memory cell array comprising a matrix of basic circuits, each of said basic circuits including: first and second word lines; first and second drain control lines; first and second main bit lines; two rows and four columns of transistor cells, said transistor cells in each of said rows having gate terminals which are coupled to a respective one of said first and second word lines, said transistor cells in each of said columns having grounded source terminals, and drain terminals coupled to a respective one of first, second, third and fourth sub-bit lines; a first drain control gate pair including first drain control gates with gate terminals coupled to said first drain control line, each of said first drain control gates further having a drain terminal coupled to a respective one of said first and third sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines; and a second drain control gate pair including second drain control gates with gate terminals coupled to said second drain control line, each of said second drain control gates further having a drain terminal coupled to a respective one of said second and fourth sub-bit lines, and a source terminal coupled to a respective one of said first and second main bit lines.
Claim 13
Dependent Claim
22 words
The memory cell array as claimed in claim 9, wherein each of said sub-bit lines is formed as a buried N+ layer.
References Cited (Backward Citations)
US4698787A
Cited
US4949309A
Cited
US5126808A
Cited
US5097444A
Cited
US5109361A
Cited
US5185718A
Cited
US5191556A
Cited
US5396459A
Cited
US5438544A
Cited
US5615153A
Cited
US5467309A
Cited
US5467307A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |