Patent US5747382A successfully refreshed from Google Patents.
US5747382A
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Two-step planarization process using chemical-mechanical polishing and reactive-ion-etching
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1996-09-24
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Granted: 1998-05-05
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Expires: 2016-09-24
Abstract
Abstract A novel method is presented to form and planarize an inter-metal-dielectric(IMD) layer of an integrated circuit with two or more levels of interconnection metallurgy. The method utilizes chemical-mechanical-polishing(CMP) followed by reactive-ion-etching(RIE) to first planarize and then etch back a deposited IMD layer. Metal line spacings of less than 1.5 microns produce voids in the IMD even when spin-on-glass(SOG) is used to partially fill the spaces prior to IMD deposition. These voids, which contain organic residues and debris, can produce eruptions of material during several subsequent processing steps. The method of this invention attenuates and de-activates these voids, rendering them completely benign. Since CMP is only used to achieve a planar surface, risks of CMP damage to alignment marks and other features are also reduced.
Inventors
- 👤 Yung-Sheng Huang
- 👤 Long-Sheng Yeou
- 👤 Ji-Chung Huang
- 👤 Chang-Song Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:13
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P95/00; H10P95/06; H10P95/062
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
142 words
A method for forming a planar insulating layer over a metal pattern having line spacings of less than 1.5 microns on a silicon wafer comprising: (a) providing a silicon wafer having a metal pattern having line spacings of less than 1.5 microns formed over its surface; (b) forming a surface smoothing layer over said silicon wafer; (c) depositing a first insulating layer over said silicon wafer whereby voids are formed within said first insulating layer over said line spacings of less than 1.5 microns; (d) removing a first thickness of said first insulating layer by chemical-mechanical-polishing(CMP) whereby the surface of said first insulating layer is planarized without exposing said voids; then (e) removing a second thickness of said first insulating layer by a dry etching technique whereby said voids are exposed; and (f) depositing a second insulating layer over said silicon wafer.
Claim 2
Independent Claim
142 words
A method for forming a planar insulating layer over a metal pattern having line spacings of less than 1.5 microns on a silicon wafer comprising: (a) providing a silicon wafer having a metal pattern having line spacings of less than 1.5 microns formed over its surface; (b) forming a surface smoothing layer over said silicon wafer; (c) depositing a first insulating layer over said silicon wafer whereby voids are formed within said first insulating layer over said line spacings of less than 1.5 microns; (d) removing a first thickness of said first insulating layer by chemical-mechanical-polishing(CMP) whereby the surface of said first insulating layer is planarized without exposing said voids; then (e) removing a second thickness of said first insulating layer by a dry etching technique whereby said voids are exposed; and (f) depositing a second insulating layer over said silicon wafer.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said surface smoothing layer is a spin-on-glass.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein said surface smoothing layer comprises silicon oxide sidewalls.
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein said first insulating layer is between about 2.2 and 3.3 microns thick.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein said first insulating layer is silicon oxide deposited by PECVD using tetraethoxy orthosilicate at a temperature of between about 350° C. and 450° C.
Claim 7
Dependent Claim
24 words
The method of claim 1 wherein said first insulating layer is selected from the group consisting of a phosphosilicate glass and a borophosphosilicate glass.
Claim 8
Dependent Claim
29 words
The method of claim 1 wherein said CMP is performed for a time to reduce the thickness of said first insulating layer to between about 6,000 to 14,000 Angstroms.
Claim 9
Dependent Claim
12 words
The method of claim 1 wherein said dry etching technique is reactive-ion-etching(RIE).
Claim 10
Dependent Claim
19 words
The method of claim 1 wherein said second insulating layer is silicon oxide deposited by PECVD using tetraethoxy orthosilicate.
Claim 11
Dependent Claim
30 words
The method of claim 9 wherein said silicon oxide is deposited at a temperature of between about 350° C. and 450° C. and is about 1,000 to 3,000 Angstroms thick.
Claim 12
Dependent Claim
24 words
The method of claim 1 wherein said second insulating layer is selected from the group consisting of a phosphosilicate glass and a borophosphosilicate glass.
Claim 13
Independent Claim
261 words
A method for forming an integrated circuit having metal line spacings of less than 1.5 microns and planarized insulating layers comprising: (a) providing a silicon wafer having integrated circuit devices formed within its surface, a level of polysilicon based device components and local polysilicon circuitry formed over its surface and an arrangement of contacts or vias imbedded in a dielectric layer over said local polysilicon circuitry; (b) depositing a conductive layer over said silicon wafer; (c) patterning and etching said conductive layer to define a level of interconnection circuitry having line spacings of less than 1.5 microns; (d) forming a surface smoothing layer over said conductive layer; (e) depositing a first insulating layer over said silicon wafer whereby voids are formed within said first insulating layer over said line spacings of less than 1.5 microns; (f) removing a first thickness of said first insulating layer by chemical-mechanical-polishing(CMP) whereby the surface of said first insulating layer is planarized without exposing said voids; then (g) removing a second thickness of said first insulating layer by a dry etching technique whereby said voids are exposed; (h) depositing a second insulating layer over said silicon wafer; (I) patterning and etching an arrangement of via openings in said first and second insulating layers thereby exposing portions of said conductive layer; (j) filling said via openings with a conductive material; (k) repeating steps (b) through (i) for each additional level of interconnecting metallurgy required by of said integrated circuit; and (I) depositing, patterning, and etching a final conductive layer for accessing external terminations of said integrated circuit.
Claim 14
Independent Claim
261 words
A method for forming an integrated circuit having metal line spacings of less than 1.5 microns and planarized insulating layers comprising: (a) providing a silicon wafer having integrated circuit devices formed within its surface, a level of polysilicon based device components and local polysilicon circuitry formed over its surface and an arrangement of contacts or vias imbedded in a dielectric layer over said local polysilicon circuitry; (b) depositing a conductive layer over said silicon wafer; (c) patterning and etching said conductive layer to define a level of interconnection circuitry having line spacings of less than 1.5 microns; (d) forming a surface smoothing layer over said conductive layer; (e) depositing a first insulating layer over said silicon wafer whereby voids are formed within said first insulating layer over said line spacings of less than 1.5 microns; (f) removing a first thickness of said first insulating layer by chemical-mechanical-polishing(CMP) whereby the surface of said first insulating layer is planarized without exposing said voids; then (g) removing a second thickness of said first insulating layer by a dry etching technique whereby said voids are exposed; (h) depositing a second insulating layer over said silicon wafer; (I) patterning and etching an arrangement of via openings in said first and second insulating layers thereby exposing portions of said conductive layer; (j) filling said via openings with a conductive material; (k) repeating steps (b) through (i) for each additional level of interconnecting metallurgy required by of said integrated circuit; and (I) depositing, patterning, and etching a final conductive layer for accessing external terminations of said integrated circuit.
Claim 15
Dependent Claim
39 words
The method of claim 12 wherein said conductive layer is selected from the group consisting of a metal layer, a metal layer with a subjacent titanium nitride layer, and a metal layer with subjacent and superjacent titanium nitride layers.
Claim 16
Dependent Claim
13 words
The method of claim 12 wherein said surface smoothing layer is a spin-on-glass.
Claim 17
Dependent Claim
14 words
The method of claim 12 wherein said surface smoothing layer comprises silicon oxide sidewalls.
Claim 18
Dependent Claim
18 words
The method of claim 12 wherein said first insulating layer is between about 2.2 and 3.3 microns thick.
Claim 19
Dependent Claim
30 words
The method of claim 12 wherein said first insulating layer is silicon oxide deposited by PECVD using tetraethoxy orthosilicate at a temperature of between about 350° C. and 450° C.
Claim 20
Dependent Claim
24 words
The method of claim 12 wherein said first insulating layer is selected from the group consisting of a phosphosilicate glass, and a borophosphosilicate glass.
Claim 21
Dependent Claim
29 words
The method of claim 12 wherein said CMP is performed for a time to reduce the thickness of said first insulating layer to between about 6,000 to 14,000 Angstroms.
Claim 22
Dependent Claim
17 words
The method of claim 12 wherein said dry etching technique is reactive-ion-etching(RIE) utilizing a gas containing tetrafluoromethane.
Claim 23
Dependent Claim
19 words
The method of claim 12 wherein said second insulating layer is silicon oxide deposited by PECVD using tetraethoxy orthosilicate.
Claim 24
Dependent Claim
30 words
The method of claim 21 wherein said silicon oxide is deposited at a temperature of between about 350° C. and 450° C. and is about 1,000 to 3,000 Angstroms thick.
Claim 25
Dependent Claim
24 words
The method of claim 14 wherein said second insulating layer is selected from the group consisting of a phosphosilicate glass and a borophosphosilicate glass.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |