US5747356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing ISRC MOSFET
Assignee: Korea Information and Communication Co Ltd
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Filing: 1996-12-05
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Granted: 1998-05-05
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Expires: 2016-12-05
Abstract
Abstract The present invention privides a method for manufacturing an ISRC MOSFET, comprising steps of forming an isolating layer through the LOCOS process, depositing a mask oxide layer, exposing only the part of silicon substrate for forming the channel and shallow junction of source/drain layers, depositing the first nitride layer over the resultant substrate, dry-etching the first nitride layer to form a nitride side-wall, forming an oxide layer being recessed into the channel, wet-etching the nitride side-wall, forming two doped layers for the shallow source/drain by an N + or P + ion-implantation, depositing the second nitride layer, dry-etching for forming a nitride side-wall, forming a P - or N - doped layer between the two doped layers, forming a gate oxide layer on the P - or N - doped layer, depositing a poly-silicon layer, forming a poly-silicon gate by a llithography process and a dry-etching process, etching away the mask oxide layer, and ion-implanting for thick source/drain junction.
Inventors
- 👤 Jong Duk Lee
- 👤 Kuk Jin Chun
- 👤 Byung Gook Park
- 👤 Jeong Ho Lyu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:56
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10P; H10P10/00; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/025; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor, comprising the steps of: forming an isolating layer on a silicon substrate through the LOCOS process in order to form the boundaries among the neighboring elements; depositing a mask oxide layer over the whole silicon substrate; exposing only the part of the silicon substrate for forming the channel and shallow junction of source/drain layers; depositing a first nitride layer over the resultant substrate; dry-etching the said first nitride layer so as to form a first nitride side-wall; forming an oxide layer being recessed into the channel by an oxidation process; wet-etching away the said first nitride side-wall; forming two doped layers for the shallow source/drain by an ion-implantation process; depositing a second nitride layer over the resultant substrate; dry-etching the said second nitride layer and the oxide layer so as to form a second nitride side-wall; forming a doped layer between the two doped layers for adjusting the threshold voltage and preventing the punchthrough phenomenon by an ion-implantation process; forming a gate oxide layer on the doped layer depositing a poly-silicon layer over the resultant substrate forming a poly-silicon gate by a lithography process and a dry-etching process; etching away the mask oxide layer; and, ion-implanting for thick source/drain junction.
Claim 2
Independent Claim
211 words
A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor, comprising the steps of: forming an isolating layer on a silicon substrate through the LOCOS process in order to form the boundaries among the neighboring elements; depositing a mask oxide layer over the whole silicon substrate; exposing only the part of the silicon substrate for forming the channel and shallow junction of source/drain layers; depositing a first nitride layer over the resultant substrate; dry-etching the said first nitride layer so as to form a first nitride side-wall; forming an oxide layer being recessed into the channel by an oxidation process; wet-etching away the said first nitride side-wall; forming two doped layers for the shallow source/drain by an ion-implantation process; depositing a second nitride layer over the resultant substrate; dry-etching the said second nitride layer and the oxide layer so as to form a second nitride side-wall; forming a doped layer between the two doped layers for adjusting the threshold voltage and preventing the punchthrough phenomenon by an ion-implantation process; forming a gate oxide layer on the doped layer depositing a poly-silicon layer over the resultant substrate forming a poly-silicon gate by a lithography process and a dry-etching process; etching away the mask oxide layer; and, ion-implanting for thick source/drain junction.
Claim 3
Dependent Claim
61 words
A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor as claimed in claim 1, wherein the said two doped layers for the shallow source/drain is formed by N + ion-implantation process and the said doped layer between the said two doped layers for adjusting the threshold voltage and preventing the punchthrough phenomenon is formed by P - ion-implantation process.
Claim 4
Dependent Claim
56 words
A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor as claimed in claim 2, wherein the distance between the said source and drain layers is determined by adjusting the gap between the nitride opposite side-walls of the said first nitride layer according to the deposition thickness and the etched amount of the said side-walls.
Claim 5
Dependent Claim
60 words
A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor as claimed in claim 1, wherein the said two doped layers for the shallow source/drain is formed by P + ion-implantation and the said doped layer between the said two doped layers for adjusting the threshold voltage and preventing the punchthrough phenomenon is formed by N - ion-implantation process.
Claim 6
Dependent Claim
56 words
A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor as claimed in claim 4, wherein the distance between the said source and drain layers is determined by adjusting the gap between the nitride opposite side-walls of the said first nitride layer according to the deposition thickness and the etched amount of the said side-walls.
Claim 7
Dependent Claim
56 words
A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor as claimed in claim 1, wherein the distance between the said source and drain layers is determined by adjusting the gap between the nitride opposite side-walls of the said first nitride layer according to the deposition thickness and the etched amount of the said side-walls.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |