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Patent US5744394A successfully refreshed from Google Patents.
US5744394A
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Method for fabricating a semiconductor device having copper layer
Assignee: Sharp Corp
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Filing: 1997-04-23
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Granted: 1998-04-28
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Expires: 2017-04-23
Abstract
Abstract A semiconductor device comprises a plurality of transistors A semiconductor device comprising a plurality of transistors formed on a semiconductor substrate and a metal interconnection layer connected to at least one of the transistors, wherein the metal interconnection layer is composed of a single layer or multi layers, the single layer or at least one layer of the multi layers being formed of copper or a copper alloy, and is connected to at least one transistor wholly or partially through a barrier layer; and at least one of the transistor is controlled on its threshold voltage by a selective ion implantation after formation of the metal interconnection layer.
Inventors
- 👤 Katsuji Iguchi
- 👤 Tsukasa Doi
- 👤 Masanori Murakami
- 👤 Takeo Oku
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:41
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/60; H10B20/65; H10D; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
135 words
A process for fabricating a semiconductor device, comprising the steps of: (i) forming a plurality of transistors on a semiconductor substrate; (ii) forming an insulating film on the resulting substrate including the transistors, followed by the formation of a contact hole and an interconnection trench in desired regions of the insulating film; (iii) forming a barrier layer in the contact hole and the interconnection trench, followed by filling the contact hole and the interconnection trench with copper or a copper alloy to form a metal interconnection layer on the barrier layer; (iv) conducting a selective ion implantation into at least one of the plurality of transistors using a resist pattern as a mask to control its threshold voltage after the completion of the interconnection layer; and (v) annealing the entire resulting substrate for activation, uniformly.
Claim 2
Dependent Claim
135 words
A process for fabricating a semiconductor device, comprising the steps of: (i) forming a plurality of transistors on a semiconductor substrate; (ii) forming an insulating film on the resulting substrate including the transistors, followed by the formation of a contact hole and an interconnection trench in desired regions of the insulating film; (iii) forming a barrier layer in the contact hole and the interconnection trench, followed by filling the contact hole and the interconnection trench with copper or a copper alloy to form a metal interconnection layer on the barrier layer; (iv) conducting a selective ion implantation into at least one of the plurality of transistors using a resist pattern as a mask to control its threshold voltage after the completion of the interconnection layer; and (v) annealing the entire resulting substrate for activation, uniformly.
Claim 3
Dependent Claim
18 words
A process of claim 1, wherein a silicide layer is formed after step (ii) and before step (iii).
Claim 4
Dependent Claim
22 words
A process of claim 1, wherein the barrier layer is composed of a tantalum compound, a titanium compound or a tungsten compound.
Claim 5
Dependent Claim
19 words
A process of claim 1 wherein an annealing temperature ranges from 700° C. to 900° C. in step (v).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-27 | 2001-10-27 | 2002-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-27 | 2005-10-27 | 2006-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-27 | 2009-10-27 | 2010-04-28 | $7700.00 | Window Closed / Lapsed |