Patent US5737568A successfully refreshed from Google Patents.
US5737568A
Expired / Lapsed
US
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Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory
Assignee: Canon Inc
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Filing: 1995-02-21
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Granted: 1998-04-07
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Expires: 2015-02-21
Abstract
Abstract In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state" when the data is shared with other cache memories, and is set to a "shared stale state" when the data in the "shared state" becomes stale by updating performed in another cache memory. Each processor monitors a transaction generated on a bus, derives a data portion from the bus when it is in the same address as the data in the "shared stale state" of its own cache memory, thereby updating the data in the address and making the state of the data a "shared state".
Inventors
- 👤 Kazumasa Hamaguchi
- 👤 Shigeki Shibayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:34
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
333 words
A method of controlling a cache memory for a local processor in a multiprocessor system, which is equipped with a shared memory and a plurality of local processors each having a respective cache memory, said method comprising the steps of: storing a state of data validity for every entry in each cache memory; monitoring, by each local processor, transactions on a system bus generated owing to read miss by other processors; generating a transaction requiring data of a shared memory address by a first local processor which has caused a read miss for the address; detecting the generated transaction by each local processor other than the first local processor; determining, by each local processor which has detected the generated transaction, whether or not an entry having a same shared memory address as the address of the generated transaction is present in its respective cache memory by comparing addresses of all entries in the cache memory with the address of the generated transaction; checking, by each local processor in which the entry of the same shared address is determined to be present, a stored state of data validity for the entry of the same shared address; outputting data of the same shared memory address to the system bus by a second local processor which has the entry of the same shared address with the state determined to be valid; deriving, by the first local processor, the output data of the same shared memory address from the system bus into its own cache memory and storing the data in an entry with a state of data validity of the entry valid; and deriving, by a third local processor which has the entry of the same shared address with the state determined to be invalid, the output data of the same shared memory address from the system bus into its respective cache memory to update the entry of the same shared memory address by the data and validating the state of data validity of the entry.
Claim 2
Independent Claim
333 words
A method of controlling a cache memory for a local processor in a multiprocessor system, which is equipped with a shared memory and a plurality of local processors each having a respective cache memory, said method comprising the steps of: storing a state of data validity for every entry in each cache memory; monitoring, by each local processor, transactions on a system bus generated owing to read miss by other processors; generating a transaction requiring data of a shared memory address by a first local processor which has caused a read miss for the address; detecting the generated transaction by each local processor other than the first local processor; determining, by each local processor which has detected the generated transaction, whether or not an entry having a same shared memory address as the address of the generated transaction is present in its respective cache memory by comparing addresses of all entries in the cache memory with the address of the generated transaction; checking, by each local processor in which the entry of the same shared address is determined to be present, a stored state of data validity for the entry of the same shared address; outputting data of the same shared memory address to the system bus by a second local processor which has the entry of the same shared address with the state determined to be valid; deriving, by the first local processor, the output data of the same shared memory address from the system bus into its own cache memory and storing the data in an entry with a state of data validity of the entry valid; and deriving, by a third local processor which has the entry of the same shared address with the state determined to be invalid, the output data of the same shared memory address from the system bus into its respective cache memory to update the entry of the same shared memory address by the data and validating the state of data validity of the entry.
Claim 3
Dependent Claim
53 words
A method according to claim 1, further comprising the steps of: notifying other processors of invalidity of the data of an entry when each processor updates the entry in its own cache memory by a writing operation; and making the state of such notified entry invalid in each cache memory having the entry.
Claim 4
Dependent Claim
30 words
A method according to claim 2, wherein each processor simultaneously updates the contents of the shared memory when updating an entry of their own cache memory by a writing operation.
Claim 5
Dependent Claim
44 words
A method according to claim 2, wherein the state of data validity includes information regarding whether or not the entry is shared with any other processors and said notifying step is executed when the state of the updated entry indicating the entry is shared.
Claim 6
Dependent Claim
37 words
A method according to claim 1, further comprising the step of setting, in each entry in each cache memory, a shared memory address with the state of data validity of each entry invalid in an initial state.
Claim 7
Dependent Claim
25 words
A method according to claim 5, wherein said resetting a shared memory address which had set based on a past history of cache memory utilization.
Claim 8
Dependent Claim
318 words
A processor constituting a multiprocessor system having a plurality of other processors interconnected via a system bus, said processor comprising: cache memory means for storing a state of data validity for every entry together with the data; generating means for generating a transaction requiring data of a shared memory address when a read miss has occurred for the address; monitoring means for monitoring transactions on the system bus generated owing to read miss by other processors; determining means for determining whether or not an entry having a same shared memory address as an address of a generated transaction detected by said monitoring means is present in said cache memory means by comparing addresses of all entries in said cache memory means with the address of the generated transaction, checking means for checking if the entry of the same shared address is determined to be present, a stored state of data validity for the entry; output means for outputting data of the same shared memory address to the system bus when the entry of the same shared address with valid state determined to be present; first deriving for deriving, a data portion output to the system bus from one of the other processor in response to the transaction, from the system bus into said cache memory means to store the data in an entry with a state of data validity of the entry valid if the transaction has generated by the own processor; and second deriving means for deriving, a data portion output to the system bus from one of the other processor in response to the transaction, from the system bus into said cache memory means to update the entry of the same shared memory address and validating the state of data validity of the updated entry if said determining means has determined that the entry of the same shared address with invalid state determined to be present.
Claim 9
Dependent Claim
318 words
A processor constituting a multiprocessor system having a plurality of other processors interconnected via a system bus, said processor comprising: cache memory means for storing a state of data validity for every entry together with the data; generating means for generating a transaction requiring data of a shared memory address when a read miss has occurred for the address; monitoring means for monitoring transactions on the system bus generated owing to read miss by other processors; determining means for determining whether or not an entry having a same shared memory address as an address of a generated transaction detected by said monitoring means is present in said cache memory means by comparing addresses of all entries in said cache memory means with the address of the generated transaction, checking means for checking if the entry of the same shared address is determined to be present, a stored state of data validity for the entry; output means for outputting data of the same shared memory address to the system bus when the entry of the same shared address with valid state determined to be present; first deriving for deriving, a data portion output to the system bus from one of the other processor in response to the transaction, from the system bus into said cache memory means to store the data in an entry with a state of data validity of the entry valid if the transaction has generated by the own processor; and second deriving means for deriving, a data portion output to the system bus from one of the other processor in response to the transaction, from the system bus into said cache memory means to update the entry of the same shared memory address and validating the state of data validity of the updated entry if said determining means has determined that the entry of the same shared address with invalid state determined to be present.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |