Analog implementation of a partial response maximum likelihood (PRML) read channel

Claim 2

An analog partial response maximum likelihood (PRML) read channel for use in a magnetic recording device, comprising: a variable gain amplifier for receiving a preamplified electronic signal corresponding to a magnetic signal detected on a magnetic media, and for applying a bias voltage for adjusting the level of said preamplified electronic signal to produce an adjusted preamplified electronic signal; a lowpass filter for filtering channel noise from said adjusted preamplified electronic signal to produce a filtered signal; an analog equalizer for receiving and smoothing the high-frequency components of the filtered signal to produce an equalized signal; a clock recovery circuit for synchronizing a read clock with the equalized signal; an analog Viterbi detector for receiving said equalized signal and producing a detected signal using maximum-likelihood sequence estimation; and a decoder/descrambler for receiving and decoding said detected signal to produce a reconstructed data signal; and wherein said read channel is implemented entirely within a single integrated circuit.

Claim 3

The read channel of claim 1, wherein said integrated circuit is fabricated in CMOS.

Claim 4

The read channel of claim 1, wherein said analog equalizer comprises an analog delay line for sampling the filtered signal, said analog delay line comprising a plurality of successive delay stages and producing at the output of each delay stage a delayed representation of the filtered signal; and an analog feedforward equalizer (FFE) for producing an equalized signal based on said delayed representations.

Claim 5

The read channel of claim 3, said analog delay line comprising an analog bucket brigade delay line with negative feedback.

Claim 6

The read channel of claim 3, said analog feedforward equalizer (FFE) comprising an analog finite impulse response (FIR) filter.

Claim 7

The read channel of claim 5, said analog finite impulse response (FIR) filter generating an equalized signal, comprising: a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving the products computed by each of said adjusted-coefficient multipliers and generating the sum of the combined products to produce the equalized signal.

Claim 8

The read channel of claim 3, said analog feedforward equalizer (FFE) 105 being adaptive.

Claim 9

The read channel of claim 3, said analog feedforward equalizer (FFE) comprising an adaptive finite impulse response (FIR) filter.

Claim 10

The read channel of claim 8, said analog finite impulse response (FIR) filter, comprising: a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving each of said computed products and for generating the equalized signal by taking the sum said products; a decision circuit for receiving said equalized signal and for generating a quantified signal; a comparator for receiving said quantified signal and said equalized signal, and for computing an error signal by computing the difference of said input equalized signal and said input quantified signal; an adaption rate multiplier for receiving said error signal and generating an adaption rate signal by adjusting said input error signal by an error adaption rate; a plurality of error multipliers, each error multiplier being associated with one each of said adjustable-coefficient multipliers, and receiving as input the delayed signal representation from its immediately succeeding delay stage to compute and produce an error product signal; a plurality of integrators, each integrator being associated with one each of said error multipliers and to the corresponding adjustable-coefficient multiplier associated with said error multiplier, and receiving as input the error product signal from its associated error multiplier to generate an integrated signal, wherein said integrated signal is input to said corresponding adjustable-coefficient multiplier for adjusting the associated weighting coefficient.

Claim 11

An analog partial response maximum likelihood (PRML) read/write channel for use in a magnetic recording device, comprising: a variable gain amplifier for receiving a preamplified electronic signal corresponding to a magnetic signal detected on a magnetic media, and for applying a bias voltage for adjusting the level of said preamplified electronic signal to produce an adjusted preamplified electronic signal; a lowpass filter for filtering channel noise from said adjusted preamplified electronic signal to produce a filtered signal; an analog equalizer for receiving and smoothing the high-frequency components of the filtered signal to produce an equalized signal; a clock recovery circuit for synchronizing a read clock with the equalized signal; an analog Viterbi detector for receiving said equalized signal and producing a detected signal using maximum-likelihood sequence estimation; and a decoder/descrambler for receiving and decoding said detected signal to produce a reconstructed data signal; and a scrambler/encoder for receiving input data to be recorded on said magnetic media and for generating an encoded signal; a clock synthesis circuit for generating a write clock for synchronous transmission of the encoded signal to said magnetic media; a write precompensation circuit for receiving said encoded signal and said write clock and for synchronously sending said encoded signal to an output port while compensating for non-linear intersymbol interference; and wherein said read channel is implemented entirely within a single integrated circuit.

Claim 12

An analog partial response maximum likelihood (PRML) read/write channel for use in a magnetic recording device, comprising: a variable gain amplifier for receiving a preamplified electronic signal corresponding to a magnetic signal detected on a magnetic media, and for applying a bias voltage for adjusting the level of said preamplified electronic signal to produce an adjusted preamplified electronic signal; a lowpass filter for filtering channel noise from said adjusted preamplified electronic signal to produce a filtered signal; an analog equalizer for receiving and smoothing the high-frequency components of the filtered signal to produce an equalized signal; a clock recovery circuit for synchronizing a read clock with the equalized signal; an analog Viterbi detector for receiving said equalized signal and producing a detected signal using maximum-likelihood sequence estimation; and a decoder/descrambler for receiving and decoding said detected signal to produce a reconstructed data signal; and a scrambler/encoder for receiving input data to be recorded on said magnetic media and for generating an encoded signal; a clock synthesis circuit for generating a write clock for synchronous transmission of the encoded signal to said magnetic media; a write precompensation circuit for receiving said encoded signal and said write clock and for synchronously sending said encoded signal to an output port while compensating for non-linear intersymbol interference; and wherein said read channel is implemented entirely within a single integrated circuit.

Claim 13

The analog read/write channel of claim 10, wherein said integrated circuit is fabricated in CMOS.

Claim 14

The analog read/write channel of claim 10, wherein said analog equalizer comprises an analog delay line for sampling the filtered signal, said analog delay line comprising a plurality of successive delay stages and producing at the output of each delay stage a delayed representation of the filtered signal; and an analog feedforward equalizer (FFE) for producing an equalized signal based on said delayed representations.

Claim 15

The analog read/write channel of claim 12, said analog delay line comprising an analog bucket brigade delay line with negative feedback.

Claim 16

The analog read/write channel of claim 12, said analog feedforward equalizer (FFE) comprising an analog finite impulse response (FIR) filter.

Claim 17

The analog read/write channel of claim 14, said analog finite impulse response (FIR) filter, comprising: a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving the products computed by each of said adjusted-coefficient multipliers and generating the sum of the combined products to produce the equalized signal.

Claim 18

The analog read/write channel of claim 12, said analog feedforward equalizer (FFE) being adaptive.

Claim 19

The analog read/write channel of claim 12, said analog feedforward equalizer (FFE) comprising an adaptive analog finite impulse response (FIR) filter.

Claim 20

The analog read/write channel of claim 17, said adaptive analog finite impulse response (FIR) filter, comprising: a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving each of said computed products and for generating the equalized signal by taking the sum said products; a decision circuit for receiving said equalized signal and for generating a quantified signal; a comparator for receiving said quantified signal and said equalized signal, and for computing an error signal by computing the difference of said input equalized signal and said input quantified signal; an adaption rate multiplier for receiving said error signal and generating an adaption rate signal by adjusting said input error signal by an error adaption rate; a plurality of error multipliers, each error multiplier being associated with one each of said adjustable-coefficient multipliers, and receiving as input the delayed signal representation from its immediately succeeding delay stage to compute and produce an error product signal; a plurality of integrators, each integrator being associated with one each of said error multipliers and to the corresponding adjustable-coefficient multiplier associated with said error multiplier, and receiving as input the error product signal from its associated error multiplier to generate an integrated signal, wherein said integrated signal is input to said corresponding adjustable-coefficient multiplier for adjusting the associated weighting coefficient.

Claim 21

The analog read/write channel of claim 10, further comprising servo circuitry for tracking capability.

Claim 22

The analog read/write channel of claim 19, wherein said servo circuitry comprises: a position error sensor for receiving said filtered signal and for determining and producing an analog position error signal; an analog-to-digital converter for receiving and converting said analog position error signal to a digital position error signal; a microprocessor interface for receiving said digital position error signal and for generating a digital servo adjustment signal; a digital-to-analog converter for receiving and converting said digital servo adjustment signal to an analog servo adjustment signal; and an output servo port wherein said analog servo adjustment signal is made accessible for external mechanical servo control.

Claim 23

An analog partial response maximum likelihood (PRML) read/write channel for use in a magnetic recording device, comprising: a variable gain amplifier for receiving a preamplified electronic signal corresponding to a magnetic signal detected on a magnetic media, and for applying a bias voltage for adjusting the level of said preamplified electronic signal to produce an adjusted preamplified electronic signal; a lowpass filter for filtering channel noise from said adjusted preamplified electronic signal to produce a filtered signal; an analog delay line for sampling and delaying successive representations of said filtered signal, said analog delay line comprising an analog bucket brigade delay line with negative feedback; an adaptive analog finite impulse response (FIR) filter, comprising a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving each of said computed products and for generating the equalized signal by taking the sum said products; a decision circuit for receiving said equalized signal and for generating a quantified signal; a comparator for receiving said quantified signal and said equalized signal, and for computing an error signal by computing the difference of said input equalized signal and said input quantified signal; an adaption rate multiplier for receiving said error signal and generating an adaption rate signal by adjusting said input error signal by an error adaption rate; a plurality of error multipliers, each error multiplier being associated with one each of said adjustable-coefficient multipliers, and receiving as input the delayed signal representation from its immediately succeeding delay stage to compute and produce an error product signal; and a plurality of integrators, each integrator being associated with one each of said error multipliers and to the corresponding adjustable-coefficient multiplier associated with said error multiplier, and receiving as input the error product signal from its associated error multiplier to generate an integrated signal, wherein said integrated signal is input to said corresponding adjustable-coefficient multiplier for adjusting the associated weighting coefficient; a clock recovery circuit for synchronizing a read clock with the equalized signal; an analog Viterbi detector for receiving said equalized signal and producing a detected signal using maximum-likelihood sequence estimation; and a decoder/descrambler for receiving and decoding said detected signal to produce a reconstructed data signal; and a scrambled/encoder for receiving input data to be recorded on said magnetic media and for generating an encoded signal; a clock synthesis circuit for generating a write clock for synchronous transmission of the encoded signal to said magnetic media; a write precompensation circuit for receiving said encoded signal and said write clock and for synchronously sending said encoded signal to an output port while compensating for non-linear intersymbol interference; and wherein said read channel is implemented entirely within a single CMOS integrated circuit.

Claim 24

An analog partial response maximum likelihood (PRML) read/write channel for use in a magnetic recording device, comprising: a variable gain amplifier for receiving a preamplified electronic signal corresponding to a magnetic signal detected on a magnetic media, and for applying a bias voltage for adjusting the level of said preamplified electronic signal to produce an adjusted preamplified electronic signal; a lowpass filter for filtering channel noise from said adjusted preamplified electronic signal to produce a filtered signal; an analog delay line for sampling and delaying successive representations of said filtered signal, said analog delay line comprising an analog bucket brigade delay line with negative feedback; an adaptive analog finite impulse response (FIR) filter, comprising a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving each of said computed products and for generating the equalized signal by taking the sum said products; a decision circuit for receiving said equalized signal and for generating a quantified signal; a comparator for receiving said quantified signal and said equalized signal, and for computing an error signal by computing the difference of said input equalized signal and said input quantified signal; an adaption rate multiplier for receiving said error signal and generating an adaption rate signal by adjusting said input error signal by an error adaption rate; a plurality of error multipliers, each error multiplier being associated with one each of said adjustable-coefficient multipliers, and receiving as input the delayed signal representation from its immediately succeeding delay stage to compute and produce an error product signal; and a plurality of integrators, each integrator being associated with one each of said error multipliers and to the corresponding adjustable-coefficient multiplier associated with said error multiplier, and receiving as input the error product signal from its associated error multiplier to generate an integrated signal, wherein said integrated signal is input to said corresponding adjustable-coefficient multiplier for adjusting the associated weighting coefficient; a clock recovery circuit for synchronizing a read clock with the equalized signal; an analog Viterbi detector for receiving said equalized signal and producing a detected signal using maximum-likelihood sequence estimation; and a decoder/descrambler for receiving and decoding said detected signal to produce a reconstructed data signal; and a scrambled/encoder for receiving input data to be recorded on said magnetic media and for generating an encoded signal; a clock synthesis circuit for generating a write clock for synchronous transmission of the encoded signal to said magnetic media; a write precompensation circuit for receiving said encoded signal and said write clock and for synchronously sending said encoded signal to an output port while compensating for non-linear intersymbol interference; and wherein said read channel is implemented entirely within a single CMOS integrated circuit.

Claim 25

An analog partial response maximum likelihood (PRML) read/write channel for use in a magnetic recording device, comprising: a variable gain amplifier for receiving a preamplified electronic signal corresponding to a magnetic signal detected on a magnetic media, and for applying a bias voltage for adjusting the level of said preamplified electronic signal to produce an adjusted preamplified electronic signal; a lowpass filter for filtering channel noise from said adjusted preamplified electronic signal to produce a filtered signal; an analog delay line for sampling said filtered signal, said analog delay line comprising a plurality of successive delay stages and producing at the output of each delay stage a delayed representation of the filtered signal, said analog delay line comprising an analog bucket brigade delay line with negative feedback; an adaptive analog finite impulse response (FIR) filter, comprising a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving each of said computed products and for generating the equalized signal by taking the sum said products; a decision circuit for receiving said equalized signal and for generating a quantified signal; a comparator for receiving said quantified signal and said equalized signal, and for computing an error signal by computing the difference of said input equalized signal and said input quantified signal; an adaption rate multiplier for receiving said error signal and generating an adaption rate signal by adjusting said input error signal by an error adaption rate; a plurality of error multipliers, each error multiplier being associated with one each of said adjustable-coefficient multipliers, and receiving as input delayed signal representation from its immediately succeeding delay stage to compute and produce an error product signal; and a plurality of integrators, each integrator being associated with one each of said error multipliers and to the corresponding adjustable-coefficient multiplier associated with said error multiplier, and receiving as input the error product signal from its associated error multiplier to generate an integrated signal, wherein said integrated signal is input to said corresponding adjustable-coefficient multiplier for adjusting the associated weighting coefficient; a clock recovery circuit for synchronizing a read clock with the equalized signal; an analog Viterbi detector for receiving said equalized signal and producing a detected signal using maximum-likelihood sequence estimation; and a decoder/descrambler for receiving and decoding said detected signal to produce a reconstructed data signal; and a scrambler/encoder for receiving input data to be recorded on said magnetic media and for generating an encoded signal; a clock synthesis circuit for generating a write clock for synchronous transmission of the encoded signal to said magnetic media; a write precompensation circuit for receiving said encoded signal and said write clock and for synchronously sending said encoded signal to an output port while compensating for non-linear intersymbol interference; and servo circuitry for tracking capability, comprising a position error sensor for receiving said filtered signal and for determining and producing an analog position error signal; an analog-to-digital converter for receiving and converting said analog position error signal to a digital position error signal; a microprocessor interface for receiving said digital position error signal and for generating a digital servo adjustment signal; a digital-to-analog converter for receiving and converting said digital servo adjustment signal to an analog servo adjustment signal; and an output servo port wherein said analog servo adjustment signal is made accessible for external mechanical servo control; and wherein said read channel is implemented entirely within a single CMOS integrated circuit.

Claim 26

An analog partial response maximum likelihood (PRML) read/write channel for use in a magnetic recording device, comprising: a variable gain amplifier for receiving a preamplified electronic signal corresponding to a magnetic signal detected on a magnetic media, and for applying a bias voltage for adjusting the level of said preamplified electronic signal to produce an adjusted preamplified electronic signal; a lowpass filter for filtering channel noise from said adjusted preamplified electronic signal to produce a filtered signal; an analog delay line for sampling said filtered signal, said analog delay line comprising a plurality of successive delay stages and producing at the output of each delay stage a delayed representation of the filtered signal, said analog delay line comprising an analog bucket brigade delay line with negative feedback; an adaptive analog finite impulse response (FIR) filter, comprising a plurality of adjustable-coefficient multipliers for receiving the delayed representations from said analog delay line, each of said adjustable-coefficient multipliers having an associated weighting coefficient and receiving one each of said delayed representations, and whereby each adjustable-coefficient multiplier computes the product of its associated weighting coefficient and its received delayed representation; a summer for receiving each of said computed products and for generating the equalized signal by taking the sum said products; a decision circuit for receiving said equalized signal and for generating a quantified signal; a comparator for receiving said quantified signal and said equalized signal, and for computing an error signal by computing the difference of said input equalized signal and said input quantified signal; an adaption rate multiplier for receiving said error signal and generating an adaption rate signal by adjusting said input error signal by an error adaption rate; a plurality of error multipliers, each error multiplier being associated with one each of said adjustable-coefficient multipliers, and receiving as input delayed signal representation from its immediately succeeding delay stage to compute and produce an error product signal; and a plurality of integrators, each integrator being associated with one each of said error multipliers and to the corresponding adjustable-coefficient multiplier associated with said error multiplier, and receiving as input the error product signal from its associated error multiplier to generate an integrated signal, wherein said integrated signal is input to said corresponding adjustable-coefficient multiplier for adjusting the associated weighting coefficient; a clock recovery circuit for synchronizing a read clock with the equalized signal; an analog Viterbi detector for receiving said equalized signal and producing a detected signal using maximum-likelihood sequence estimation; and a decoder/descrambler for receiving and decoding said detected signal to produce a reconstructed data signal; and a scrambler/encoder for receiving input data to be recorded on said magnetic media and for generating an encoded signal; a clock synthesis circuit for generating a write clock for synchronous transmission of the encoded signal to said magnetic media; a write precompensation circuit for receiving said encoded signal and said write clock and for synchronously sending said encoded signal to an output port while compensating for non-linear intersymbol interference; and servo circuitry for tracking capability, comprising a position error sensor for receiving said filtered signal and for determining and producing an analog position error signal; an analog-to-digital converter for receiving and converting said analog position error signal to a digital position error signal; a microprocessor interface for receiving said digital position error signal and for generating a digital servo adjustment signal; a digital-to-analog converter for receiving and converting said digital servo adjustment signal to an analog servo adjustment signal; and an output servo port wherein said analog servo adjustment signal is made accessible for external mechanical servo control; and wherein said read channel is implemented entirely within a single CMOS integrated circuit.