Reduced complexity EPR4 post-processor for sampled data detection

Claim 2

An extended partial response, class IV (EPR4) detector within a partial response, class IV (PR4) equalized sampled data detection channel and comprising: a PR4 Viterbi detector connected to receive digital samples from the PR4 equalized sampled data detection channel for producing an estimated sequence of coded digital information values corresponding to a determined path through a PR4 trellis and for producing other path information relating to other paths through the PR4 trellis, a post-processor connected to the PR4 Viterbi detector and to the PR4 equalized sampled data detection channel and including: a PR4 path storage circuit for receiving and storing the estimated sequence of coded digital information values which specifies a PR4 path comprising a sequence of states through an EPR4 trellis, an error-event selection circuit for receiving the other path information from the PR4 Viterbi detector for selecting non-overlapping error-events from a set of error-events, and a path correction circuit connected to the PR4 path storage circuit and to the error-events selection circuit for correcting said non-overlapping error-events deviating from the PR4 path through the EPR4 trellis, and for putting out a corrected estimated sequence of coded digital information values.

Claim 3

The EPR4 detector set forth in claim 1 wherein the PR4 Viterbi detector is connected to receive odd and even digital samples from the PR4 equalized sampled data detection channel and comprises two bit-wise interleaved (1-D') Viterbi detectors, each said interleaved Viterbi detector putting out an estimated input sequence corresponding to a path through a (1-D') trellis and other path information relating to other paths through the (1-D') trellis.

Claim 4

The EPR4 detector set forth in claim 2 wherein each of the (1-D') interleaved Viterbi detectors puts out binary merge symbols indicating one of presence and absence of diverging survivor paths within said each (1-D') interleaved Viterbi detector as said other path information relating to other paths through the (1-D') trellis.

Claim 5

The EPR4 detector set forth in claim 3 wherein the error-event selection circuit within the post-processor includes: a metrics calculation and comparison circuit for calculating and comparing metrics for the set of error-events, a non-overlapping error-events identification circuit responsive to the metrics calculation and comparison circuit for identifying the non-overlapping error events to correct by comparing a calculated metric for an error-event within the set of error-events to a metric for an error-event within the set of error-events and corresponding to a best-error-event observed over a time window.

Claim 6

The EPR4 detector set forth in claim 4 wherein the set of error-events for which metrics are calculated by the metrics calculation and comparison circuit comprises one of the following: from a series of type B minimum distance error-events, a best type B minimum distance error-event ending at each state of the sequence of states along the PR4 path through the EPR4 trellis; from a series of type B minimum distance error-events, a best type B minimum distance error-event; and, from a series of type A minimum distance error-events, a best type A minimum distance error-event ending at each state of the sequence of states along the PR4 path through the EPR4 trellis; and, from a series of type B minimum distance error-events, a best type B minimum distance error-event; and, from a series of type A error-events, a best type A error-event ending at each state of the sequence of states along the PR4 path through the EPR4 trellis wherein the best type A error-event is not necessarily a minimum distance error-event.

Claim 7

The EPR4 detector set forth in claim 5 wherein the estimated sequence of coded digital information values is in accordance with a rate 16/17 (d=0, G=6/I=7) modulation code, and wherein the series of type B minimum distance error-events corresponds to mistaking the following input sequences: ______________________________________ 1 and 0 1 × 1 and 0 × 0 1 × 1 × 1 and 0 × 0 × 0 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 × 1 × and 0 × 0 × 0 × 0 × 0 × 0 × 0 × 0 ______________________________________ where x indicates a "don't care" state; and wherein the series of type A error-events corresponds to mistaking the following input sequences: ______________________________________ 101 and 010 1010 and 0101 10101 and 01010 101010 and 010101 1010101 and 0101010 10101010 and 01010101. ______________________________________

Claim 8

The EPR4 detector set forth in claim 3 wherein the PR4 path storage circuit includes: a merge bits memory connected to receive and delay merge bits from the two bit-wise interleaved (1-D') Viterbi detectors, and a PR4 decision memory connected to receive and delay estimated input symbols from the two bit-wise interleaved (1-D') Viterbi detectors; wherein the error-event selection circuit includes: an error-event validation circuit connected to the merge memory and to the PR4 decision memory for validating error-events, an error-event metric generation circuit connected to the merge memory, the PR4 decision memory and to the error-event validation circuit for calculating odd and even interleave error metric signals, and an error-event comparison circuit for comparing the odd and even interleave error metric signals and for determining a current best error-event as identified by the largest error-event metric; and, wherein the path correction circuit includes: an update best error-event circuit for calculating a current difference metric from the current best error-event and for comparing the current difference metric with a best difference metric within a timing window, and for selecting and saving an updated best error-event difference metric, and a best error-event correction circuit connected to the merge bits memory, the PR4 decision memory and the update best error-event circuit for correcting all symbol errors occurring within an error-event identified by the updated best error-event difference metric, and for putting out corrected symbols as the corrected estimated sequence of coded digital information values.

Claim 9

The EPR4 detector set forth in claim 1 wherein the sampled data detection channel includes an encoder and a precoder for encoding incoming digital information values into the sequence of coded digital information values in accordance with a rate 16/17 (d=0, G=6/I=7) modulation code.

Claim 10

A digital information storage and retrieval channel including an encoder and a precoder for encoding information values into a sequence of coded digital information values in accordance with a predetermined modulation code, a data write channel for writing the coded digital information values to a magnetic data storage medium, a partial response, class IV (PR4) equalized sampled data detection channel for receiving a signal stream from the magnetic data storage medium and including a PR4 equalizer circuit for equalizing the signal stream to a PR4 spectrum, and a digital sampler for providing synchronous digital samples from the equalized signal stream and further including: a PR4 Viterbi detector connected to receive the synchronous digital samples for producing an estimated sequence of the coded digital information values and for producing other path information relating to other paths through a PR4 trellis, a post-processor connected to the PR4 Viterbi detector and to the PR4 equalized sampled data detection channel and including: a PR4 path storage circuit for receiving and storing the estimated sequence of coded digital information values which corresponds to a PR4 path comprising a sequence of states through an extended partial response, class IV (EPR4) trellis, an error-event selection circuit for receiving the other path information from the PR4 Viterbi detector for generating non-overlapping error-events from a set of error-events deviating from the PR4 path through the EPR4 trellis stored in the PR4 path storage circuit, a path correction circuit connected to the PR4 path storage circuit and to the error-event selection circuit for correcting said non-overlapping error-events deviating from the PR4 path through the EPR4 trellis, and for putting out a corrected estimated sequence of coded digital information values.

Claim 11

A digital information storage and retrieval channel including an encoder and a precoder for encoding information values into a sequence of coded digital information values in accordance with a predetermined modulation code, a data write channel for writing the coded digital information values to a magnetic data storage medium, a partial response, class IV (PR4) equalized sampled data detection channel for receiving a signal stream from the magnetic data storage medium and including a PR4 equalizer circuit for equalizing the signal stream to a PR4 spectrum, and a digital sampler for providing synchronous digital samples from the equalized signal stream and further including: a PR4 Viterbi detector connected to receive the synchronous digital samples for producing an estimated sequence of the coded digital information values and for producing other path information relating to other paths through a PR4 trellis, a post-processor connected to the PR4 Viterbi detector and to the PR4 equalized sampled data detection channel and including: a PR4 path storage circuit for receiving and storing the estimated sequence of coded digital information values which corresponds to a PR4 path comprising a sequence of states through an extended partial response, class IV (EPR4) trellis, an error-event selection circuit for receiving the other path information from the PR4 Viterbi detector for generating non-overlapping error-events from a set of error-events deviating from the PR4 path through the EPR4 trellis stored in the PR4 path storage circuit, a path correction circuit connected to the PR4 path storage circuit and to the error-event selection circuit for correcting said non-overlapping error-events deviating from the PR4 path through the EPR4 trellis, and for putting out a corrected estimated sequence of coded digital information values.

Claim 12

The digital information storage and retrieval channel set forth in claim 9 wherein the PR4 equalized sampled data detection channel further comprises a digital finite impulse response filter connected between the digital sampler and the PR4 viterbi detector, and wherein the post-processor is connected to an output of the digital finite impulse response filter.

Claim 13

The digital information storage and retrieval channel set forth in claim 9 wherein the predetermined modulation code comprises a rate 16/17 (d=0, G=6/I=7) modulation code.

Claim 14

The digital information storage and retrieval channel set forth in claim 9 further comprising a postcoder and a decoder for decoding the corrected estimated sequence of coded digital information values in accordance with an inverse of the rate 16/17 (d=0, G=6/I=7) modulation code.

Claim 15

The digital information storage and retrieval channel set forth in claim 9 wherein the PR4 Viterbi detector is connected to receive odd and even digital samples from the PR4 equalized sampled data detection channel and comprises two bit-wise (1-D') interleaved Viterbi detectors, each said (1-D') interleaved Viterbi detector putting out an estimated input sequence corresponding to a path through a (1-D') trellis and other path information relating to other paths through the (1-D') trellis.

Claim 16

The digital information storage and retrieval channel set forth in claim 13 wherein each of the (1-D') interleaved Viterbi detectors puts out binary merge symbols indicating one of presence and absence of diverging survivor paths within each said (1-D') interleaved Viterbi detector as said other path information relating to other paths through the (1-D') trellis.

Claim 17

A digital information storage and retrieval channel set forth in claim 14 wherein the error-events selection circuit within the post-processor includes: a metrics calculation and comparison circuit for calculating and comparing metrics for the set of error-events, a non-overlapping error-events identification circuit responsive to the metrics calculation and comparison circuit for identifying the non-overlapping error events to correct by comparing a calculated metric for an error-event within the set of error-events to a metric for an error-event corresponding to a best-error-event observed over a time window.

Claim 18

The digital information storage and retrieval channel set forth in claim 15 wherein the set of error-events for which metrics are calculated by the metrics calculation and comparison circuit comprises one of the following: from a series of type B minimum distance error-events, a best type B minimum distance error-event ending at each state in a sequence of states along the PR4 path through the EPR4 trellis, from a series of type B minimum distance error-events, a best type-B minimum distance error-event and from a series of type A minimum distance error events, a best type A minimum distance error event ending at each state in the sequence of states along the PR4 path through the EPR4 trellis, and from a series of type B minimum distance error-events, a best type B minimum distance error-event and from a series of type A error events, a best type A error-event ending at each state in the sequence of states along the PR4 path through the EPR4 trellis wherein the best type A error-event is not a minimum distance error-event.

Claim 19

The digital information storage and retrieval channel set forth in claim 16 wherein the estimated sequence of coded digital information values is in accordance with a rate 16/17 (d=0, G=6/I-7) modulation code, and wherein the series of type B minimum distance error-events corresponds to mistaking the following input sequences: __________________________________________________________________________ 1 and 0 1 × 1 and 0 × 0 1 × 1 × 1 and 0 × 0 × 0 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 × 1 × and 0 × 0 × 0 × 0 × 0 × 0 × 0 × 0 __________________________________________________________________________ where x indicates a "don't care" state; and wherein the series of type A error-events corresponds to mistaking the following input sequences: ______________________________________ 101 and 010 1010 and 0101 10101 and 01010 101010 and 010101 1010101 and 0101010 10101010 and 01010101. ______________________________________

Claim 20

The digital information storage and retrieval channel set forth in claim 14 wherein the PR4 path storage circuit includes: a merge bits memory connected to receive and delay merge bits from the two bit-wise interleaved (1-D') Viterbi detectors, and a PR4 decision memory connected to receive and delay write current samples from the two bit-wise interleaved (1-D') Viterbi detectors; wherein the error-event selection circuit includes: an error-event validation circuit connected to the merge memory and to the PR4 decision memory for validating error-events, an error-event metric generation circuit connected to the merge memory, the PR4 decision memory and to the error-event validation circuit for calculating odd and even interleave error metric signals, and an error-event comparison circuit for comparing the odd and even interleave error metric signals and for determining a current best error-event as identified by the largest error-event metric; and, wherein the path correction circuit includes: an update best error-event circuit for calculating a current difference metric from the current best error-event and for comparing the current difference metric with a best difference metric within a timing window, and for selecting and saving an updated best difference metric, and a best error-event correction circuit connected to the merge bits memory, the PR4 decision memory and the update best error-event circuit for correcting all symbol errors occurring within an error-event identified by the updated best error-event difference metric, and for putting out corrected symbols as the corrected estimated sequence of coded digital information values.

Claim 21

An extended partial response, class IV (EPR4) detection method within a partial response, class IV (PR4) equalized sampled data detection channel comprising the steps of: receiving digital samples from the PR4 equalized sampled data detection channel into a PR4 Viterbi detector and producing within the PR4 Viterbi detector an estimated sequence of coded digital information values corresponding to a determined path through a PR4 trellis and other path information relating to other paths through the PR4 trellis, post-processing the estimated sequence of coded digital information values and the other path information within a post-processor connected to the PR4 Viterbi detector and to the PR4 equalized sampled data detection channel in accordance with the further steps of: receiving and storing the estimated sequence of coded digital information values which corresponds to a PR4 path comprising a sequence of states through an EPR4 trellis within a PR4 path storage circuit, receiving the other path information from the PR4 Viterbi detector and generating non-overlapping error-events from a set of error-events deviating from the PR4 path through the EPR4 trellis stored in the PR4 path storage circuit within an error-event selection circuit, and correcting said non-overlapping error-events deviating from the PR4 path through the EPR4 trellis within a path correction circuit connected to the PR4 path storage circuit and to the error-event selection circuit and putting out a corrected estimated sequence of coded digital information values.

Claim 22

An extended partial response, class IV (EPR4) detection method within a partial response, class IV (PR4) equalized sampled data detection channel comprising the steps of: receiving digital samples from the PR4 equalized sampled data detection channel into a PR4 Viterbi detector and producing within the PR4 Viterbi detector an estimated sequence of coded digital information values corresponding to a determined path through a PR4 trellis and other path information relating to other paths through the PR4 trellis, post-processing the estimated sequence of coded digital information values and the other path information within a post-processor connected to the PR4 Viterbi detector and to the PR4 equalized sampled data detection channel in accordance with the further steps of: receiving and storing the estimated sequence of coded digital information values which corresponds to a PR4 path comprising a sequence of states through an EPR4 trellis within a PR4 path storage circuit, receiving the other path information from the PR4 Viterbi detector and generating non-overlapping error-events from a set of error-events deviating from the PR4 path through the EPR4 trellis stored in the PR4 path storage circuit within an error-event selection circuit, and correcting said non-overlapping error-events deviating from the PR4 path through the EPR4 trellis within a path correction circuit connected to the PR4 path storage circuit and to the error-event selection circuit and putting out a corrected estimated sequence of coded digital information values.

Claim 23

The EPR4 detection method set forth in claim 19 comprising the further steps of receiving odd and even digital samples from the PR4 equalized sampled data detection channel into two bit-wise (1-D') interleaved Viterbi detectors and putting out an estimated input sequence corresponding to a path through a (1-D') trellis and other path information relating to other paths through the (1-D') trellis from each bit-wise (1-D') interleaved Viterbi detector.

Claim 24

The EPR4 detection method set forth in claim 20 comprising the further steps of putting out from each bit-wise (1-D') interleaved Viterbi detector binary merge symbols indicating one of presence and absence of diverging survivor paths as said other path information relating to other paths through the (1-D') trellis.

Claim 25

The EPR4 detection method set forth in claim 21 comprising the further steps of calculating and comparing metrics for the set of error-events within the error-event selection circuit within the post-processor, and identifying the non-overlapping error events to correct by comparing a metric for an error-event within the set of error-events to a metric for an error-event corresponding to a best-error-event observed over a time window within a non-overlapping error-events identification circuit within the post-processor.

Claim 26

The EPR4 detection method set forth in claim 22 wherein the set of error-events for which metrics are calculated by the metrics calculation and comparison step comprises the step of determining one of the following: from a series of type B minimum distance error-events, a best type B minimum distance error-event ending at each state in the sequence of states along the PR4 path through the EPR4 trellis, from a series of type B minimum distance error-events a best type B minimum distance error-event and from a series of type A minimum distance error-events a best type A minimum distance error event ending at each state in the sequence of states along the PR4 path through the EPR4 trellis, and from a series of type B minimum distance error-events a best type B minimum distance error-event and from a series of type A error-events a best type A error-event ending at each state in the sequence of states along the PR4 path through the EPR4 trellis wherein the best type A error-event is not necessarily a minimum distance error-event.

Claim 27

The EPR4 detection method set forth in claim 23 wherein the estimated sequence of coded digital information values is in accordance with a rate 16/17 (d=0, G=6/I=7) modulation code, and wherein the step of determining the series of minimum distance type B error-events comprises the step of determining mistaking of the following input sequences: __________________________________________________________________________ 1 and 0 1 × 1 and 0 × 0 1 × 1 × 1 and 0 × 0 × 0 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 × 1 and 0 × 0 × 0 × 0 × 0 × 0 × 0 1 × 1 × 1 × 1 × 1 × 1 × 1 × and 0 × 0 × 0 × 0 × 0 × 0 × 0 × 0 __________________________________________________________________________ where x indicates a "don't care" state; and wherein the step of determining the series of type A error-events comprises the step of determining mistaking of the following input sequences: ______________________________________ 101 and 010 1010 and 0101 10101 and 01010 101010 and 010101 1010101 and 0101010 10101010 and 01010101. ______________________________________

Claim 28

The EPR4 detection method set forth in claim 19 comprising the further step of encoding digital information values coming into the PR4 equalized sampled data detection channel into the sequence of coded digital information values in accordance with a rate 16/17 (d=0, G=6/I=7) modulation code.

Claim 29

The EPR4 detection method set forth in claim 25 comprising the further step of decoding the corrected estimated sequence of coded digital information values in accordance with an inverse of the rate 16/17 (d=0, G=6/I=7) modulation code.