Scan test circuit for use in semiconductor integrated circuit

Claim 1

A scan test circuit in a semiconductor integrated circuit, comprising: a circuit block having a scan latch for shifting a scan-in signal and holding the scan-in signal at each clock timing in response to an enable signal, the scan latch shifting the hold signal and outputting the hold signal as scan-out at the clock timing in response to the enable signal, the scan test circuit further comprising: scan message input and output means for receiving a scan message signal including scan mode type information and scan-in data connected to each other in series, and for transmitting the scan-out signal as the scan message signal in response to an output control signal, the scan mode type information signal being operative to designate a scan mode, and the scan-in data serving as a fault diagnostic test data; message separating means for separating the scan mode type information from the scan message signal, and for separating the scan-in data as the scan-in signal from the scan message signal; and a mode decoder for supplying the enable signal to the circuit block when the scan mode type information is indicative of a scan-in mode, and for supplying the enable signal to the circuit block and supplying the output control signal to the scan message input and output means when the scan mode type information is indicative of a scan-out mode.