US5731222A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Externally connected thin electronic circuit having recessed bonding pads
Assignee: OL Security LLC
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Filing: 1995-08-01
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Granted: 1998-03-24
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Expires: 2015-08-01
Abstract
Abstract Recesses (46) are etched into the finished peripheral boundaries of a structure formed of a generally planar electronic circuit (40) on an upper surface (42) of a wafer (44). Bonding pads (48) are deposited in the recesses (46) and interconnected to the electronic circuit (40). External leads (52) are attached to the bonding pads (48), such that the external leads (52) lie below the plane of the electronic circuit (40).
Inventors
- 👤 Gerard T. Malloy
- 👤 Joe B. Tyra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:51
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/951; Y; Y10; Y10S; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
189 words
A method for fabricating an externally connected electronic circuit, comprising the steps of: providing a generally planar electronic circuit on an upper surface of a wafer having a finished peripheral boundary; forming at least one recess at the finished peripheral boundary of the wafer, the step of forming at least one recess including the steps of depositing an etch-resistant layer overlying the upper surface of the wafer, patterning the etch-resistant layer to define at least one region where the recess is to be located, and etching material from the wafer in the at least one patterned region; removing the etch-resistant layer; forming a dielectric film over the upper surface of the wafer and patterning the dielectric film; forming a plurality of bonding pads in the at least one recess and connecting the bonding pads to the planar electronic circuit, the step of forming and connecting being accomplished simultaneously and including the step of depositing an electrical conductor at the locations whereat at least one bonding pad and an electrical interconnection between the bonding pad and the electronic circuit are required; and wire bonding external leads to the bonding pads.
Claim 2
Independent Claim
189 words
A method for fabricating an externally connected electronic circuit, comprising the steps of: providing a generally planar electronic circuit on an upper surface of a wafer having a finished peripheral boundary; forming at least one recess at the finished peripheral boundary of the wafer, the step of forming at least one recess including the steps of depositing an etch-resistant layer overlying the upper surface of the wafer, patterning the etch-resistant layer to define at least one region where the recess is to be located, and etching material from the wafer in the at least one patterned region; removing the etch-resistant layer; forming a dielectric film over the upper surface of the wafer and patterning the dielectric film; forming a plurality of bonding pads in the at least one recess and connecting the bonding pads to the planar electronic circuit, the step of forming and connecting being accomplished simultaneously and including the step of depositing an electrical conductor at the locations whereat at least one bonding pad and an electrical interconnection between the bonding pad and the electronic circuit are required; and wire bonding external leads to the bonding pads.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein the step of etching material includes the step of anisotropically etching the wafer.
Claim 4
Dependent Claim
25 words
The method of claim 2, wherein the step of anisotropically etching the wafer includes the step of chemically etching the wafer with an anisotropic etch.
Claim 5
Dependent Claim
27 words
The method of claim 1, further including an additional step, after the step of wire bonding, of encapsulating the structure resulting after the step of wire bonding.
Claim 6
Dependent Claim
39 words
The method of claim 1, wherein the step of providing a generally planar electronic circuit on an upper surface of a wafer having a finished peripheral boundary includes the step of providing a silicon wafer in a 100! orientation.
Claim 7
Dependent Claim
107 words
The method of claim 1, wherein the step of providing a generally planar electronic circuit on an upper surface of a wafer having a finished peripheral boundary includes the step of fabricating a plurality of electronic circuits on an oversize wafer, so that the finished peripheral boundary does not coincide with a peripheral boundary of the oversize wafer, and including the additional step, after the step of forming a plurality of bonding pads, of dicing the oversize wafer to form a plurality of diced wafers such that the finished peripheral boundary of each of the plurality of electronic circuits lies at the boundary of each diced wafer.
Claim 8
Dependent Claim
12 words
An externally connected electronic circuit prepared by the method of claim 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-23 | 2001-09-22 | 2002-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-23 | 2005-09-22 | 2006-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-23 | 2009-09-22 | 2010-03-24 | $7700.00 | Window Closed / Lapsed |