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US5729709A
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Memory controller with burst addressing circuit
Assignee: Intel Corp
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Filing: 1996-03-21
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Granted: 1998-03-17
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Expires: 2016-03-21
Abstract
Abstract An improved memory controller of a computer system is described. The computer system includes a microprocessor and a memory coupled to the memory controller that controls access to the memory. An interface circuit is coupled to the microprocessor for receiving a first address to access the memory. The memory includes a first memory bank and a second memory bank. A memory control circuit is coupled to the interface circuit for generating control signals to access the memory. An address generation circuit is coupled to receive the first address from the interface circuit for generating a first memory address and a second memory address in accordance with the first address to access the memory during a burst access to the memory from the microprocessor. The address generation circuit further comprises circuitry for generating and applying the first memory address sequentially to the first and second memory banks and circuitry for generating and applying the second memory address sequentially to the first and second memory banks. The second memory address is generated by inverting at least the lowest order address bit in the first memory address Access time of the burst access is minimized by using the first microprocessor memory address and generating a second memory address therefrom.
Inventors
- 👤 Jeffrey F. Harness
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1647; G06F13/20; G06F13/28; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1042; Y; Y10; Y10S; Y10S715/00; Y10S715/974
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
116 words
A memory controller, comprising: (a) an input that receives a first memory address for a memory having a first memory bank and a second memory bank; and (b) an address and control circuit coupled to the input and the memory, wherein the address and control circuit generates a first column address strobe signal for the first memory bank, a second column address strobe signal for the second memory bank, and a sequence of memory addresses in response to the first memory address, wherein the address and control circuit alternately generates the first and second column address strobe signals to enable each of the first and second memory banks to latch the sequence of memory addresses, respectively.
Claim 2
Dependent Claim
116 words
A memory controller, comprising: (a) an input that receives a first memory address for a memory having a first memory bank and a second memory bank; and (b) an address and control circuit coupled to the input and the memory, wherein the address and control circuit generates a first column address strobe signal for the first memory bank, a second column address strobe signal for the second memory bank, and a sequence of memory addresses in response to the first memory address, wherein the address and control circuit alternately generates the first and second column address strobe signals to enable each of the first and second memory banks to latch the sequence of memory addresses, respectively.
Claim 3
Dependent Claim
31 words
The memory controller of claim 1, wherein the sequence of memory addresses provided by the address and control circuit includes the first memory address and at least a second memory address.
Claim 4
Dependent Claim
65 words
The memory controller of claim 2, wherein each of the first and second memory addresses includes a sequence of row address bits and column address bits, each sequence ranging from a most significant bit to a least significant bit, wherein the least significant column address bit in the second memory address is inverted from the least significant column address bit in the first memory address.
Claim 5
Dependent Claim
36 words
The memory controller of claim 3, wherein the address and control circuit provides the sequence of memory addresses in an order such that the first memory address is provided before the second memory address is provided.
Claim 6
Dependent Claim
122 words
The memory controller of claim 4, wherein the address and control circuit further comprises (a) a first output circuit coupled to the input, the first output circuit providing the most significant column address bits in the first and second memory addresses to the first and second memory bank; (b) a second output circuit coupled to the input, the second output circuit providing the least significant column address bit in the first and second memory addresses to the first and second memory bank; and (c) a timing circuit that sequentially asserts the first and second column address strobe signals to enable the first and second memory banks, respectively, to sequentially latch a combination of bits provided by the first and second output circuits.
Claim 7
Dependent Claim
51 words
The memory controller of claim 5, wherein the second output circuit is coupled to the input of the memory controller to receive a first column address bit for controlling the state of the least significant column address bit provided by the second output circuit to the first and second memory banks.
Claim 8
Dependent Claim
40 words
The memory controller of claim 6, wherein the second output circuit provides the least significant column address bit of the first memory address by setting that bit equal to the first column address bit received by the second output circuit.
Claim 9
Dependent Claim
43 words
The memory controller of claim 7, wherein the second output circuit provides the least significant column address bit of the second memory address by setting that bit equal to the inverse of the first column address bit received by the second output circuit.
Claim 10
Dependent Claim
72 words
The memory controller of claim 8, wherein the second output circuit first provides the least significant column address bit in the first memory address to the first and second memory banks and then sequentially provides the least significant column address bit in the second memory address to the first and second memory banks, the sequence being controlled by the state of a second column address bit received by the second output circuit.
Claim 11
Dependent Claim
27 words
The memory controller of claim 9, wherein the first column address bit received by the second output circuit is the A3 bit in the first memory address.
Claim 12
Dependent Claim
27 words
The memory controller of claim 9, wherein the second column address bit received by the second output circuit is the A2 bit in the first memory address.
Claim 13
Dependent Claim
31 words
The memory controller of claim 9, wherein the most significant column address bits of the first memory address provided by the first output circuit are provided throughout a burst read cycle.
Claim 14
Dependent Claim
48 words
The memory controller of claim 1, wherein the memory controller is coupled to a microprocessor by a host bus and to a system master by a system bus, and wherein the first memory address received by the memory controller is generated by the microprocessor or the system master.
Claim 15
Dependent Claim
32 words
The memory controller of claim 1 wherein the address and control circuit alternately generates the first and second column address strobe signals during a first burst cycle and a second burst cycle.
Claim 16
Dependent Claim
53 words
The memory controller of claim 1 wherein the address and control circuit asserts the first column address strobe signal and deasserts the second column address strobe signal during a first burst cycle, and deasserts the first column address strobe signal and asserts the second column address strobe signal during a second burst cycle.
Claim 17
Dependent Claim
242 words
A computer memory controller for generating memory control signals and a sequence of memory addresses in response to a first address received by the memory controller, comprising: (a) an interface circuit that receives the first address having row address bits and column address bits for addressing a memory having an odd memory bank and an even memory bank; (b) an address generation circuit coupled to the interface circuit, the address generation circuit receiving at least one of the column address bits and providing a sequence of odd column address bits and a sequence of even column address bits to the odd and even memory banks, respectively; and (c) a control circuit coupled to the interface circuit, the control circuit receiving at least a subset of the column address bits of the first address and providing (1) the subset of column address bits to the odd memory bank and the even memory bank and (2) an odd column address strobe signal to the odd memory bank and an even column address strobe signal to the even memory bank, the odd and even column address strobe signals being alternately asserted to enable the odd and even memory banks to latch combinations of bits output by the address generation circuit and the control circuit, wherein the row address bits and the combinations of bits collectively comprise the sequence of memory addresses, and the odd and even column address strobe signals represent the memory control signals.
Claim 18
Dependent Claim
242 words
A computer memory controller for generating memory control signals and a sequence of memory addresses in response to a first address received by the memory controller, comprising: (a) an interface circuit that receives the first address having row address bits and column address bits for addressing a memory having an odd memory bank and an even memory bank; (b) an address generation circuit coupled to the interface circuit, the address generation circuit receiving at least one of the column address bits and providing a sequence of odd column address bits and a sequence of even column address bits to the odd and even memory banks, respectively; and (c) a control circuit coupled to the interface circuit, the control circuit receiving at least a subset of the column address bits of the first address and providing (1) the subset of column address bits to the odd memory bank and the even memory bank and (2) an odd column address strobe signal to the odd memory bank and an even column address strobe signal to the even memory bank, the odd and even column address strobe signals being alternately asserted to enable the odd and even memory banks to latch combinations of bits output by the address generation circuit and the control circuit, wherein the row address bits and the combinations of bits collectively comprise the sequence of memory addresses, and the odd and even column address strobe signals represent the memory control signals.
Claim 19
Dependent Claim
35 words
The memory controller of claim 16, wherein the odd and even column address bits provided by the address generation circuit comprise the least significant column address bits provided to the odd and even memory banks.
Claim 20
Dependent Claim
33 words
The memory controller of claim 17, wherein the subset of column address bits provided by the control circuit comprises the most significant column address bits provided to the odd and even memory banks.
Claim 21
Dependent Claim
48 words
The memory controller of claim 18, wherein the sequence of odd column address bits and the sequence of even column address bits provided by the address generation circuit begin with a bit having the same state as a first column address bit received by the address generation circuit.
Claim 22
Dependent Claim
35 words
The memory controller of claim 19, wherein the address generation circuit includes a state circuit for controlling the state of the sequence of odd and even column address bits output by the address generation circuit.
Claim 23
Dependent Claim
44 words
The memory controller of claim 20, wherein a second column address bit received by the address generation circuit is coupled to the state circuit for controlling the state of the sequence of odd and even column address bits output by the address generation circuit.
Claim 24
Dependent Claim
26 words
The memory controller of claim 21, wherein the first column address bit received by the address generation circuit is the A3 bit of the first address.
Claim 25
Dependent Claim
26 words
The memory controller of claim 22, wherein the second column address bit received by the address generation circuit is the A2 bit of the first address.
Claim 26
Dependent Claim
47 words
The memory controller of claim 16, wherein the memory controller is coupled to a microprocessor by a host bus and to a system master by a system bus, and wherein the first address received by the memory controller is generated by the microprocessor or the system master.
Claim 27
Dependent Claim
36 words
The computer memory controller of claim 16 wherein the control circuit alternately provides the odd column address strobe signal during a first burst cycle and the even column address strobe signal during a second burst cycle.
Claim 28
Dependent Claim
52 words
The computer memory controller of claim 16 wherein the control circuit asserts the odd column address strobe signal and deasserts the even column address strobe signal during a first burst cycle, and deasserts the odd column address strobe signal and asserts the even column address strobe signal during a second burst cycle.
Claim 29
Independent Claim
115 words
A method of operating a memory controller, comprising the steps of: (a) receiving at an input of the memory controller a first memory address to a memory having a first memory bank and a second memory bank; and (b) outputting to the memory from an address generation and control circuit a first column address strobe signal for the first memory bank, a second column address strobe signal for the second memory bank, and a sequence of memory addresses in response to the first memory address, wherein the first and second column address strobe signals are alternately output to enable each of the first and second memory banks to latch the sequence of memory addresses, respectively.
Claim 30
Independent Claim
115 words
A method of operating a memory controller, comprising the steps of: (a) receiving at an input of the memory controller a first memory address to a memory having a first memory bank and a second memory bank; and (b) outputting to the memory from an address generation and control circuit a first column address strobe signal for the first memory bank, a second column address strobe signal for the second memory bank, and a sequence of memory addresses in response to the first memory address, wherein the first and second column address strobe signals are alternately output to enable each of the first and second memory banks to latch the sequence of memory addresses, respectively.
Claim 31
Dependent Claim
23 words
The method of claim 27, wherein the sequence of memory addresses includes the first memory address and at least a second memory address.
Claim 32
Dependent Claim
64 words
The method of claim 28, wherein each of the first and second memory addresses includes a sequence of row address bits and column address bits, each sequence ranging from a most significant bit to a least significant bit, wherein the least significant column address bit in the second memory address is inverted from the least significant column address bit in the first memory address.
Claim 33
Dependent Claim
35 words
The method of claim 29, further comprising the step of outputting the sequence of memory addresses to the memory in an order such that the first memory address is output before the second memory address.
Claim 34
Dependent Claim
94 words
The method of claim 30, wherein the step (b) further comprises the steps of (i) outputting the most significant column address bits in the first and second memory addresses to the first and second memory bank; (ii) outputting the least significant column address bit in the first and second memory addresses to the first and second memory bank; and (iii) sequentially asserting the first and second column address strobe signals to enable the first and second memory bank, respectively, to sequentially latch a combination of bits output to the first and second memory banks.
Claim 35
Dependent Claim
79 words
The method of claim 31, wherein the step (b)(ii) further comprises the steps of (A) setting the least significant column address bit of the first memory address to a state equal to the state of the first column address bit in the first memory address; (B) setting the least significant column address bit of the second memory address to a state equal to the inverse of the state of the first column address bit in the first memory address.
Claim 36
Dependent Claim
74 words
The method of claim 31, wherein the step (b)(ii) further comprises the steps of (i) outputting the least significant column address bit in the first memory address to the first and second memory bank; and (ii) sequentially outputting the least significant column address bit in the second memory address to the first and second memory bank, the sequence being controlled by the state of a second column address bit in the first memory address.
Claim 37
Dependent Claim
66 words
The method of claim 27 wherein step (b) further comprises the steps of: (i) asserting the first column address strobe signal during a first burst cycle; (ii) deasserting the second column address strobe signal during the first burst cycle; (iii) deasserting the first column address strobe signal during a second burst cycle; and (iv) asserting the second column address strobe signal during the second burst cycle.
Claim 38
Dependent Claim
115 words
A memory controller, comprising: (a) an input that receives a memory address for a memory having a first memory bank and a second memory bank; and (b) an address and control circuit coupled to the input and the memory, wherein the address and control circuit generates a first enable signal for the first memory bank and a second enable signal for the second memory bank in response to the first memory address, wherein the address and control circuit alternately generates the first and second enable signals to enable each of the first and second memory banks, respectively, to be addressed by the first memory address and to output data addressed by the first memory address.
Claim 39
Dependent Claim
115 words
A memory controller, comprising: (a) an input that receives a memory address for a memory having a first memory bank and a second memory bank; and (b) an address and control circuit coupled to the input and the memory, wherein the address and control circuit generates a first enable signal for the first memory bank and a second enable signal for the second memory bank in response to the first memory address, wherein the address and control circuit alternately generates the first and second enable signals to enable each of the first and second memory banks, respectively, to be addressed by the first memory address and to output data addressed by the first memory address.
Claim 40
Dependent Claim
38 words
The memory controller of claim 35, wherein the address and control circuit generates a sequence of memory addresses that include the first memory address and at least a second memory address in response to the first memory address.
Claim 41
Dependent Claim
36 words
The memory controller of claim 36, wherein the address and control circuit provides the sequence of memory addresses in an order such that the first memory address is provided before the second memory address is provided.
Claim 42
Dependent Claim
48 words
The memory controller of claim 35, wherein the memory controller is coupled to a microprocessor by a host bus and to a system master by a system bus, and wherein the first memory address received by the memory controller is generated by the microprocessor or the system master.
Claim 43
Dependent Claim
31 words
The memory controller of claim 35 wherein the control circuit alternately generates the first enable signal in a first burst cycle and the second enable signal in a second burst cycle.
Claim 44
Dependent Claim
43 words
The memory controller of claim 35 wherein the control circuit asserts the first enable signal and deasserts the second enable signal during a first burst cycle, and deasserts the first enable signal and asserts the second enable signal during a second burst cycle.
Claim 45
Independent Claim
115 words
A method of operating a memory controller, comprising the steps of: (a) receiving at an input of the memory controller a first memory address to a memory having a first memory bank and a second memory bank; and (b) outputting to the memory from an address generation and control circuit a first enable signal for the first memory bank and a second enable signal for the second memory bank in response to the first memory address, wherein the first and second enable signals are alternately output to enable each of the first and second memory banks, respectively, to be addressed by the first memory address and to output data addressed by the first memory address.
Claim 46
Independent Claim
115 words
A method of operating a memory controller, comprising the steps of: (a) receiving at an input of the memory controller a first memory address to a memory having a first memory bank and a second memory bank; and (b) outputting to the memory from an address generation and control circuit a first enable signal for the first memory bank and a second enable signal for the second memory bank in response to the first memory address, wherein the first and second enable signals are alternately output to enable each of the first and second memory banks, respectively, to be addressed by the first memory address and to output data addressed by the first memory address.
Claim 47
Dependent Claim
44 words
The method of claim 41, further including the step of outputting to the memory a sequence of memory addresses in response to the first memory address, wherein the sequence of memory addresses include the first memory address and at least a second memory address.
Claim 48
Dependent Claim
35 words
The method of claim 42, further comprising the step of outputting the sequence of memory addresses to the memory in an order such that the first memory address is output before the second memory address.
Claim 49
Dependent Claim
58 words
The method of claim 41 wherein step (b) further comprises the steps of: (i) asserting the first enable signal during a first burst cycle; (ii) deasserting the second enable signal during the first burst cycle; (iii) deasserting the first enable signal during a second burst cycle; and (iv) asserting the second enable signal during the second burst cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-16 | 2001-09-15 | 2002-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-16 | 2005-09-15 | 2006-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-16 | 2009-09-15 | 2010-03-17 | $7700.00 | Window Closed / Lapsed |