Patent US5726580A successfully refreshed from Google Patents.
US5726580A
Expired / Lapsed
US
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Universal wafer carrier for wafer level die burn-in
Assignee: Micron Technology Inc
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Filing: 1996-05-24
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Granted: 1998-03-10
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Expires: 2016-05-24
Abstract
Abstract A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a die cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, it is possible to establish interconnection between the single die or separate and package the dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
Inventors
- 👤 Alan G. Wood
- 👤 Tim J. Corbett
- 👤 Warren M. Farnworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:02
CPC Classifications
H; H10; H10W; H10W99/00; G; G01; G01R; G01R1/00; G01R1/02; G01R1/04; G01R1/0408; G01R1/0433; G01R1/0483; G01R1/0491; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R31/2865; G01R31/2867; G01R31/2886; G01R31/2889; G01R31/2893; H05; H05K; H05K3/00; H05K3/40; H05K3/4007; H10P; H10P74/00; H10P74/23; H10P74/232; H10W70/00; H10W70/60; H10W70/67; H10W70/68; G01R1/0441; G01R1/0466; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/0735; G01R3/00; G01R31/282; G01R31/2831; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0133; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0347; H05K2201/0364; H05K2201/0367; H05K2201/0388; H05K2201/0394; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09481; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/03; H05K2203/0307; H05K2203/07; H05K2203/0703; H05K2203/0723; H05K3/0058; H05K3/0067; H05K3/42; H05K3/423; H10W70/681; H10W90/00; H10W90/20; H10W90/24; H10W90/701; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
266 words
Wafer level testing apparatus for testing a plurality of semiconductor devices fabricated from a wafer and in die form while the dice remain on the wafer, said wafer level testing apparatus for use in performing electrical tests in a manner similar to that accomplished with discrete packaged semiconductor devices, said wafer level testing apparatus comprising: a) a first plate having a wafer-receiving cavity therein, the wafer-receiving cavity being dimensioned to receive a semiconductor wafer therein; b) a second plate mating with the first plate; c) alignment means for aligning the first plate with the second plate; d) a plurality of wafer contacting conductors extending from one of the first and second plates, the wafer contacting conductors extending to contacts to establish electrical communication with contact locations on the semiconductor wafer, said one of the first and the second plate having the plurality of wafer contacting conductors extending therefrom being fabricated on a substrate which is at least partially rigid, whereby the plurality of wafer contacting conductors being positioned so that, when the first plate and the second plate are aligned by the alignment means and the semiconductor wafer is positioned in the wafer-receiving cavity, the contacts are in alignment with contact locations on the semiconductor wafer; e) connector terminals in electrical communication with the plurality of wafer contacting conductors, the connector terminals being mounted to said one of the first and second plates; and f) means to bias the wafer in the wafer-receiving cavity into contact with at least one of the plurality or wafer contacting conductors after the first and second plates have been mated.
Claim 2
Dependent Claim
266 words
Wafer level testing apparatus for testing a plurality of semiconductor devices fabricated from a wafer and in die form while the dice remain on the wafer, said wafer level testing apparatus for use in performing electrical tests in a manner similar to that accomplished with discrete packaged semiconductor devices, said wafer level testing apparatus comprising: a) a first plate having a wafer-receiving cavity therein, the wafer-receiving cavity being dimensioned to receive a semiconductor wafer therein; b) a second plate mating with the first plate; c) alignment means for aligning the first plate with the second plate; d) a plurality of wafer contacting conductors extending from one of the first and second plates, the wafer contacting conductors extending to contacts to establish electrical communication with contact locations on the semiconductor wafer, said one of the first and the second plate having the plurality of wafer contacting conductors extending therefrom being fabricated on a substrate which is at least partially rigid, whereby the plurality of wafer contacting conductors being positioned so that, when the first plate and the second plate are aligned by the alignment means and the semiconductor wafer is positioned in the wafer-receiving cavity, the contacts are in alignment with contact locations on the semiconductor wafer; e) connector terminals in electrical communication with the plurality of wafer contacting conductors, the connector terminals being mounted to said one of the first and second plates; and f) means to bias the wafer in the wafer-receiving cavity into contact with at least one of the plurality or wafer contacting conductors after the first and second plates have been mated.
Claim 3
Dependent Claim
23 words
Wafer level testing apparatus as described in claim 1, wherein said means to bias the wafer in the wafer-receiving cavity includes air pressure.
Claim 4
Dependent Claim
47 words
Wafer level testing apparatus as described in claim 1, wherein the plurality of wafer contacting conductors includes a plurality of contacts which extend from a substrate to engage with conductive contacts at the contact locations on the wafer after the first and second plates have been mated.
Claim 5
Dependent Claim
52 words
Wafer level testing apparatus as described in claim 1, further comprising; the wafer-receiving cavity having a biased platform therein, the biased platform exerting a biasing force caused by the biasing means against the wafer which is sufficiently uniform to cause the wafer to establish contact with the plurality of wafer contacting conductors.
Claim 6
Dependent Claim
37 words
Wafer level testing apparatus as described in claim 4, wherein the plurality of wafer contacting conductors includes a plurality of rigid conductors which extend into the wafer-receiving cavity after the first and second plates have been mated.
Claim 7
Dependent Claim
37 words
Wafer level testing apparatus as described in claim 1, wherein the plurality of wafer contacting conductors includes a plurality of flexible rods which extend into the wafer-receiving cavity after the first and second plates have been mated.
Claim 8
Dependent Claim
67 words
Wafer level testing apparatus as described in claim 1, wherein the plurality of wafer contacting conductors includes an elastomeric conductor which extends into the wafer-receiving cavity after the first and second plates have been mated, the elastomeric conductor having portions thereof electrically contacting at least one of the plurality of wafer contacting conductors and electrically contacting at least one of the contact locations on the semiconductor wafer.
Claim 9
Dependent Claim
52 words
Wafer level testing apparatus as described in claim 1, wherein the plurality of wafer contacting conductors including a plurality of contact pads which are in alignment with the wafer-receiving cavity after the first and second plates have been mated, said alignment corresponding to a pattern of contact locations on the semiconductor wafer.
Claim 10
Dependent Claim
59 words
Wafer level testing apparatus as described in claim 1, further comprising: a platform corresponding to the wafer-receiving cavity, the platform being biased by the means to bias the wafer in the wafer-receiving cavity, the means to bias the wafer including an elastomeric polymer so as to cause the wafer to establish contact with the plurality of wafer contacting conductors.
Claim 11
Dependent Claim
310 words
Wafer carrier for testing a plurality of semiconductor devices fabricated from a wafer and in die form while the dice remain on the wafer, said wafer carrier for use in performing electrical tests in a manner similar to that accomplished with discrete packages semiconductor devices, said wafer carrier comprising: a) a first plate having a wafer-receiving cavity therein, the wafer-receiving cavity being dimensioned to receive a semiconductor wafer therein; b) a second plate mating with the first plate; c) alignment means for aligning the first plate with the second plate; d) a plurality of wafer contacting conductors extending from one of the first plate or the second plate, the wafer contacting conductors extending to contacts to establish electrical communication with contact locations on the semiconductor wafer, said one of the first plate or the second plate having the plurality of wafer contacting conductors extending therefrom being fabricated on a rigid substrate, the plurality of wafer contacting conductors being positioned so that, when the first plate and the second plate are aligned by the alignment means and the semiconductor wafer is positioned in the wafer-receiving cavity, the contacts are in alignment with contact locations on the semiconductor wafer; e) means located in the wafer-receiving cavity for exerting biasing force against the wafer to establish contact with the respective plurality of wafer contacting conductors on said one of the first plate and the second plate having the plurality of wafer contacting conductors therein, the wafer-receiving cavity securing the wafer from movement within the wafer-receiving cavity sufficiently to maintain the plurality of wafer contacting conductors in said alignment with contact locations on the wafer; and f) connector terminals in an electrical communication with the plurality of wafer contacting conductors, the connector terminals being mounted to said one of the first plate and second plate having the plurality of wafer contacting conductors extending therefrom.
Claim 12
Dependent Claim
310 words
Wafer carrier for testing a plurality of semiconductor devices fabricated from a wafer and in die form while the dice remain on the wafer, said wafer carrier for use in performing electrical tests in a manner similar to that accomplished with discrete packages semiconductor devices, said wafer carrier comprising: a) a first plate having a wafer-receiving cavity therein, the wafer-receiving cavity being dimensioned to receive a semiconductor wafer therein; b) a second plate mating with the first plate; c) alignment means for aligning the first plate with the second plate; d) a plurality of wafer contacting conductors extending from one of the first plate or the second plate, the wafer contacting conductors extending to contacts to establish electrical communication with contact locations on the semiconductor wafer, said one of the first plate or the second plate having the plurality of wafer contacting conductors extending therefrom being fabricated on a rigid substrate, the plurality of wafer contacting conductors being positioned so that, when the first plate and the second plate are aligned by the alignment means and the semiconductor wafer is positioned in the wafer-receiving cavity, the contacts are in alignment with contact locations on the semiconductor wafer; e) means located in the wafer-receiving cavity for exerting biasing force against the wafer to establish contact with the respective plurality of wafer contacting conductors on said one of the first plate and the second plate having the plurality of wafer contacting conductors therein, the wafer-receiving cavity securing the wafer from movement within the wafer-receiving cavity sufficiently to maintain the plurality of wafer contacting conductors in said alignment with contact locations on the wafer; and f) connector terminals in an electrical communication with the plurality of wafer contacting conductors, the connector terminals being mounted to said one of the first plate and second plate having the plurality of wafer contacting conductors extending therefrom.
Claim 13
Dependent Claim
44 words
Wafer carrier as described in claim 10, wherein the plurality of wafer contacting conductors includes a plurality of contacts which extend from a substrate to engage with conductive contacts at contact locations on the wafer after the first and second plates have been mated.
Claim 14
Dependent Claim
33 words
Wafer carrier as described in claim 10, wherein the plurality of wafer contacting conductors includes a rigid conductor which extends into the wafer-receiving cavity after the first and second plates have been mated.
Claim 15
Dependent Claim
35 words
Wafer carrier as described in claim 10, wherein the plurality of wafer contacting conductors including a plurality of flexible rods which extend into the wafer-receiving cavity after the first and second plates have been mated.
Claim 16
Dependent Claim
33 words
Wafer carrier as described in claim 10, wherein the plurality of wafer contacting conductors includes an elastomeric conductor which extends into the wafer-receiving cavity after the first and second plates have been mated.
Claim 17
Dependent Claim
49 words
Wafer carrier as described in claim 10, wherein the plurality of wafer contacting conductors including a plurality of contact pads which are in alignment with the wafer-receiving cavity after the first and second plates have been mated, said alignment corresponding to a pattern of contact locations on the wafer.
Claim 18
Dependent Claim
66 words
Wafer carrier as described in claim 10, further comprising: a platform corresponding to the wafer-receiving cavity, the platform being biased by an elastomer polymer forming the means located in the wafer-receiving cavity for exerting biasing force against the wafer to establish contact with the respective plurality of wafer contact conductors so as to cause the wafer to establish contact with the plurality of wafer contacting conductors.
Claim 19
Dependent Claim
258 words
Wafer level testing apparatus for testing a plurality of semiconductor devices fabricated from a wafer and in die form while the dice remain on the wafer, said wafer carrier for use in performing electrical tests in a manner similar to that accomplished with discrete packaged semiconductor devices, said wafer carrier comprising: a) a first plate having a wafer-receiving cavity therein, the wafer-receiving cavity being dimensioned to receive a semiconductor wafer therein; b) a second plate mating with the first plate; c) alignment means for aligning the first plate with the second plate; d) a plurality of wafer contacting conductors extending from one of the first and second plates, the plurality of wafer contacting conductors extending to contacts to establish electrical communication with contact locations on the semiconductor wafer, said one of the first plate or the second plate having the plurality of wafer contacting conductors extending therefrom being fabricated on a substrate which is at least partially flexible, the plurality of wafer contacting conductors being positioned so that when the first plate and the second plate are aligned by the alignment means and the semiconductor wafer is positioned in the wafer-receiving cavity, the contact are in alignment with contact locations on the semiconductor wafer; e) connector terminals in an electrical communication with the plurality of wafer contacting conductors, the connector terminals being mounted to the one of said plates; and f) means to bias the wafer in the wafer-receiving cavity into contact with the plurality of wafer contacting conductors after the first and second plates have been mated.
Claim 20
Dependent Claim
258 words
Wafer level testing apparatus for testing a plurality of semiconductor devices fabricated from a wafer and in die form while the dice remain on the wafer, said wafer carrier for use in performing electrical tests in a manner similar to that accomplished with discrete packaged semiconductor devices, said wafer carrier comprising: a) a first plate having a wafer-receiving cavity therein, the wafer-receiving cavity being dimensioned to receive a semiconductor wafer therein; b) a second plate mating with the first plate; c) alignment means for aligning the first plate with the second plate; d) a plurality of wafer contacting conductors extending from one of the first and second plates, the plurality of wafer contacting conductors extending to contacts to establish electrical communication with contact locations on the semiconductor wafer, said one of the first plate or the second plate having the plurality of wafer contacting conductors extending therefrom being fabricated on a substrate which is at least partially flexible, the plurality of wafer contacting conductors being positioned so that when the first plate and the second plate are aligned by the alignment means and the semiconductor wafer is positioned in the wafer-receiving cavity, the contact are in alignment with contact locations on the semiconductor wafer; e) connector terminals in an electrical communication with the plurality of wafer contacting conductors, the connector terminals being mounted to the one of said plates; and f) means to bias the wafer in the wafer-receiving cavity into contact with the plurality of wafer contacting conductors after the first and second plates have been mated.
Claim 21
Dependent Claim
23 words
Wafer level testing apparatus as described in claim 17, wherein said means to bias the wafer in the wafer-receiving cavity includes air pressure.
Claim 22
Dependent Claim
44 words
Wafer level testing apparatus as described in claim 17, wherein the plurality of wafer contacting conductors includes a plurality of contacts which extend from a substrate to engage with conductive contact locations on the wafer after the first and second plates have been mated.
Claim 23
Dependent Claim
52 words
Wafer level testing apparatus as described in claim 17, further comprising: the wafer-receiving cavity having a biased platform therein, the biased platform exerting a biasing force caused by the biasing means against the wafer which is sufficiently uniform to cause the wafer to establish contact with the plurality of wafer contacting conductors.
Claim 24
Dependent Claim
33 words
Wafer level testing apparatus as described in claim 20, wherein the wafer contacting conductors include a rigid conductor which extends into the wafer-receiving cavity after the first and second plates have been mated.
Claim 25
Dependent Claim
35 words
Wafer level testing apparatus as described in claim 17, wherein the plurality of wafer contacting conductors including a rigid conductor which extends into the wafer-receiving cavity after the first and second plates have been mated.
Claim 26
Dependent Claim
37 words
Wafer level testing apparatus as described in claim 17, wherein the plurality of wafer contacting conductors includes a plurality of flexible rods which extend into the wafer-receiving cavity after the first and second plates have been mated.
Claim 27
Dependent Claim
35 words
Wafer level testing apparatus as described in claim 17, wherein the plurality of wafer contacting conductors includes an elastomeric conductor which extends into the wafer-receiving cavity after the first and second plates have been mated.
Claim 28
Dependent Claim
51 words
Wafer level testing apparatus as described in claim 17, wherein the plurality of wafer contacting conductors includes a plurality of contact pads which are in aligment with the wafer-receiving cavity after the first and second plates have been mated, said alignment corresponding to a pattern of contact locations on the wafer.
Claim 29
Dependent Claim
71 words
Wafer level testing apparatus as described in claim 17, further comprising: a platform corresponding to the wafer-receiving cavity, the platform being biased by an elastomeric polymer forming the means located in the wafer-receiving cavity for exerting biasing force against the wafer with the plurality of wafer contacting conductors after the first and second plates have been mated so as to cause the wafer to establish contact with the wafer contacting conductors.
References Cited (Backward Citations)
US4766371A
Cited
JPS62293629A
Cited
US4924589A
Cited
US4994735A
Cited
US5020219A
Cited
US5034685A
Cited
US5103557A
Cited
US4899107A
Cited
US4918374A
Cited
US4968931A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-09 | 2001-09-08 | 2002-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-09 | 2005-09-08 | 2006-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-09 | 2009-09-08 | 2010-03-10 | $7700.00 | Window Closed / Lapsed |