US5724592A — Method and apparatus for managing active power co…

Claim 1

Independent Claim 96 words

A flash electrically-erasable programmable read only memory (EEPROM) device comprising: a flash EEPROM array; a memory which stores indications of power modes in which the flash EEPROM device can be read from or written to; a configuration register which stores a power mode configuration value, provided by a host processor, which corresponds to one of the power mode indications stored in the memory; and a microprocessor, responsive to commands from the host processor, for reading the configuration register and for controlling operations related to the flash EEPROM array in accordance with the power mode configuration value.

Claim 2

Dependent Claim 96 words

A flash electrically-erasable programmable read only memory (EEPROM) device comprising: a flash EEPROM array; a memory which stores indications of power modes in which the flash EEPROM device can be read from or written to; a configuration register which stores a power mode configuration value, provided by a host processor, which corresponds to one of the power mode indications stored in the memory; and a microprocessor, responsive to commands from the host processor, for reading the configuration register and for controlling operations related to the flash EEPROM array in accordance with the power mode configuration value.

Claim 3

Dependent Claim 39 words

A flash EEPROM device as claimed in claim 1 further comprising a memory which stores processes for selecting a mode for accessing the flash EEPROM array during read and write operations in accordance with the power mode configuration values.

Claim 4

Dependent Claim 29 words

A flash EEPROM device as claimed in claim 2 in which the mode for accessing the flash EEPROM array during read and write operations selects bytewide or wordwide accesses.

Claim 5

Dependent Claim 37 words

A flash EEPROM device as claimed in claim 1 further comprising a memory which stores processes for selecting operations which may be run concurrently by the flash EEPROM device in accordance with the power mode configuration values.

Claim 6

Dependent Claim 32 words

A flash EEPROM device as claimed in claim 1 further comprising a memory which stores processes for selecting a clock frequency for the microprocessor in accordance with the power mode configuration values.

Claim 7

Dependent Claim 45 words

A flash EEPROM device as claimed in claim 1 in which the microprocessor is also for controlling reading from and writing to the flash EEPROM array in each of the power modes in which the flash EEPROM device can be read from or written to.

Claim 8

Dependent Claim 46 words

A flash EEPROM device as claimed in claim 1, wherein: said microprocessor selects a clock signal for the operations related to said flash EEPROM array, and wherein said clock signal is selectably divided from a system clock signal in accordance with said power mode configuration values.

Claim 9

Dependent Claim 37 words

A flash EEPROM device as claimed in claim 1, wherein: said microprocessor selects either a byte-wide or a word-wide access mode for operations related to said flash EEPROM array in accordance with said power mode configuration values.

Claim 10

Dependent Claim 109 words

A microprocessor controlled storage device comprising: memory array means; microprocessor means, external to the memory array means, for controlling operations related to the memory array means; means for storing indications of power modes in which the storage device can be read from or written to; means for detecting indications, from a host processor, of power modes available; means for setting a power mode configuration which corresponds to one of the power mode indications stored in the means for storing; and means for responding to a set power mode configuration and for reducing power use of individual components of the storage device in accordance with the set power mode configuration.

Claim 11

Dependent Claim 109 words

A microprocessor controlled storage device comprising: memory array means; microprocessor means, external to the memory array means, for controlling operations related to the memory array means; means for storing indications of power modes in which the storage device can be read from or written to; means for detecting indications, from a host processor, of power modes available; means for setting a power mode configuration which corresponds to one of the power mode indications stored in the means for storing; and means for responding to a set power mode configuration and for reducing power use of individual components of the storage device in accordance with the set power mode configuration.

Claim 12

Dependent Claim 25 words

A microprocessor controlled storage device as claimed in claim 9 in which the means for storing indications of power modes comprises: attribute memory storage means.

Claim 13

Dependent Claim 24 words

A microprocessor controlled storage device as claimed in claim 9 in which the means for responding includes firmware processes run by the microprocessor means.

Claim 14

Dependent Claim 30 words

A microprocessor controlled storage device as claimed in claim 11 in which the firmware processes run by the microprocessor means selects a clock frequency for operation of the microprocessor means.

Claim 15

Dependent Claim 34 words

A microprocessor controlled storage device as claimed in claim 11 in which the firmware processes run by the microprocessor means selects a mode for accessing the memory array means during read and write operations.

Claim 16

Dependent Claim 31 words

A microprocessor controlled storage device as claimed in claim 11 in which the firmware processes run by the microprocessor means selects which operations may be run concurrently by the storage device.

Claim 17

Dependent Claim 112 words

A computer system comprising: a central processing unit; a system bus; main memory; and a flash electrically-erasable programmable read only memory (EEPROM) device comprising: a flash EEPROM array, a memory which stores indications of power modes in which the flash EEPROM device can be read from or written to, a configuration register which stores a power mode configuration value, provided by the central processing unit, which corresponds to one of the power mode indications stored in the memory, and a microprocessor, responsive to commands from the central processing unit, for reading the configuration register and for controlling operations related to the flash EEPROM array in accordance with the power mode configuration value.

Claim 18

Dependent Claim 112 words

A computer system comprising: a central processing unit; a system bus; main memory; and a flash electrically-erasable programmable read only memory (EEPROM) device comprising: a flash EEPROM array, a memory which stores indications of power modes in which the flash EEPROM device can be read from or written to, a configuration register which stores a power mode configuration value, provided by the central processing unit, which corresponds to one of the power mode indications stored in the memory, and a microprocessor, responsive to commands from the central processing unit, for reading the configuration register and for controlling operations related to the flash EEPROM array in accordance with the power mode configuration value.

Claim 19

Dependent Claim 44 words

A computer system as claimed in claim 15 in which the flash EEPROM device further comprises a memory which stores processes for selecting a mode for accessing the flash EEPROM array during read and write operations in accordance with the power mode configuration values.

Claim 20

Dependent Claim 28 words

A computer system as claimed in claim 16 in which the mode for accessing the flash EEPROM array during read and write operations selects bytewide or wordwide accesses.

Claim 21

Dependent Claim 42 words

A computer system as claimed in claim 15 in which the flash EEPROM device further comprises a memory which stores processes for selecting operations which may be run concurrently by the flash EEPROM device in accordance with the power mode configuration values.

Claim 22

Dependent Claim 37 words

A computer system as claimed in claim 15 in which the flash EEPROM device further comprises a memory which stores processes for selecting a clock frequency for the microprocessor in accordance with the power mode configuration values.

Claim 23

Independent Claim 98 words

A method of managing power in a microprocessor controlled storage device, the method comprising the steps of: (a) identifying a plurality of operating power modes in which the storage device can be read from or written to; (b) selecting an operating power mode from the plurality of operating power modes; (c) storing, responsive to a host processor, an indication of the selected operating power mode; and (d) reducing power use of individual components of the storage device in accordance with the selected operating power mode, such that the storage device may still be read from and written to.

Claim 24

Independent Claim 98 words

A method of managing power in a microprocessor controlled storage device, the method comprising the steps of: (a) identifying a plurality of operating power modes in which the storage device can be read from or written to; (b) selecting an operating power mode from the plurality of operating power modes; (c) storing, responsive to a host processor, an indication of the selected operating power mode; and (d) reducing power use of individual components of the storage device in accordance with the selected operating power mode, such that the storage device may still be read from and written to.

Claim 25

Dependent Claim 55 words

A method of managing power in a microprocessor controlled storage device as claimed in claim 20 in which the reducing step (d) comprises the steps of: selecting a clock frequency for a microprocessor controlling the storage device; and selecting a mode for accessing a memory array of the storage device during read and write operations.

Claim 26

Dependent Claim 32 words

A method of managing power in a microprocessor controlled storage device as claimed in claim 20 comprising a further step of initiating operation of the storage device in a lowest power mode.

Claim 27

Dependent Claim 35 words

A method of managing power in a microprocessor controlled storage device as claimed in claim 22 in which the reducing step (d) occurs only after a first operational command is provided to the storage device.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-03-02	2001-09-01	2002-03-03	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-03-02	2005-09-01	2006-03-03	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-03-02	2009-09-01	2010-03-03	$7700.00	Window Closed / Lapsed

Method and apparatus for managing active power consumption in a microprocessor controlled storage device

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