Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: an internal circuit having a node; first means for receiving a supply voltage; second means for receiving a second voltage; voltage detecting means for detecting a value of the supply voltage; voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the voltage step down means operating in either the first mode or in the second mode in response to the voltage detecting means; and means, coupled between the first receiving means and the node and responsive to the voltage detecting means, for selectively applying a voltage to the node at times when the voltage stepdown means is operating in the second mode.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said means for selectively applying a voltage includes a MOSFET.

Claim 4

A semiconductor integrated circuit according to claim 1, wherein said voltage detecting means includes means for generating a control signal that is concurrently provided to said voltage stepdown means and said means for selectively applying a voltage.

Claim 5

A semiconductor integrated circuit according to claim 1, wherein said voltage detecting means includes means for generating a first control signal provided to said voltage stepdown means and a second control signal provided to said means for selectively applying a voltage.

Claim 6

A semiconductor integrated circuit according to claim 4, wherein said voltage detecting means includes means for generating the first control signal so that said voltage stepdown means operates in the first mode when the supply voltage value is larger than a first voltage value and operates in the second mode when the supply voltage value is smaller than the first voltage value, and for generating the second control signal so that the means for selectively applying a voltage applies a voltage to the node when the supply voltage value is smaller than a second voltage value larger than the said first voltage value.

Claim 7

A semiconductor integrated circuit, adapted for receiving a chip selection signal, comprising: an internal circuit having a node; first means for receiving a supply voltage; second means for receiving a second voltage; voltage detecting means for detecting a value of the supply voltage to generate a control signal; first voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the first voltage step down means operating in either the first mode or in the second mode in response to the control signal and the chip selection signal; second voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the second voltage step down means operating in either the first mode or in the second mode in response to the control signal; and means, coupled between the first receiving means and the node and responsive to the voltage detecting means, for selectively applying a voltage to the node at times when the first and second voltage stepdown means are both operating in the second mode.

Claim 8

A semiconductor integrated circuit, adapted for receiving a chip selection signal, comprising: an internal circuit having a node; first means for receiving a supply voltage; second means for receiving a second voltage; voltage detecting means for detecting a value of the supply voltage to generate a control signal; first voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the first voltage step down means operating in either the first mode or in the second mode in response to the control signal and the chip selection signal; second voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the second voltage step down means operating in either the first mode or in the second mode in response to the control signal; and means, coupled between the first receiving means and the node and responsive to the voltage detecting means, for selectively applying a voltage to the node at times when the first and second voltage stepdown means are both operating in the second mode.

Claim 9

A semiconductor integrated circuit according to claim 6, wherein said means for selectively applying a voltage includes a MOSFET.

Claim 10

A semiconductor integrated circuit according to claim 6, wherein said first and second voltage stepdown means have the same circuit construction, and the current supply capacity of said first voltage stepdown means is larger than that of said second voltage stepdown means.

Claim 11

A semiconductor integrated circuit, adapted for receiving a chip selection signal, comprising: an internal circuit having a node; first means for receiving a power supply voltage; second means for receiving a reference voltage; voltage detecting means for detecting a value of the supply voltage to generate a first control signal to indicate whether the value of the supply voltage is less than a first predetermined value and a second control signal to indicate whether the value of the supply voltage is less than a second predetermined value; first voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the first voltage stepdown means operating in either the first mode or in the second mode in response to the first control signal and the chip selection signal; second voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the second voltage stepdown means operating in either the first mode or in the second mode in response to the first control signal; and means, coupled between the first receiving means and the node and responsive to the second control signal, for selectively applying a voltage to the node in response to the second control signal.

Claim 12

A semiconductor integrated circuit, adapted for receiving a chip selection signal, comprising: an internal circuit having a node; first means for receiving a power supply voltage; second means for receiving a reference voltage; voltage detecting means for detecting a value of the supply voltage to generate a first control signal to indicate whether the value of the supply voltage is less than a first predetermined value and a second control signal to indicate whether the value of the supply voltage is less than a second predetermined value; first voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the first voltage stepdown means operating in either the first mode or in the second mode in response to the first control signal and the chip selection signal; second voltage stepdown means for operating in one of a first mode for stepping down the supply voltage to apply a voltage to the node while conducting a first amount of current through the second receiving means, and a second mode while conducting an amount of current less than the first amount of current through the second receiving means, the second voltage stepdown means operating in either the first mode or in the second mode in response to the first control signal; and means, coupled between the first receiving means and the node and responsive to the second control signal, for selectively applying a voltage to the node in response to the second control signal.

Claim 13

A semiconductor integrated circuit according to claim 9, wherein said means for selectively applying a voltage includes a MOSFET.

Claim 14

A semiconductor integrated circuit according to claim 9, wherein said first and second voltage stepdown means have the same circuit construction, and the current supply capacity of said first voltage stepdown means is larger than that of said second voltage stepdown means.

Claim 15

A semiconductor integrated circuit according to claim 9, further comprising means for generating two voltages whose values are different from each other, and wherein said voltage detecting means includes first and second control signal generator circuits which compares the supply voltage value with the respective ones of said two voltages to generate said first and second control signals.

Claim 18

The method of claim 13, in which the closing step includes the substep of closing the switch at times when the detecting step detects that the value of the supply voltage is less than the second predetermined value, the second predetermined value being greater than the first predetermined value.

Claim 19

The method of claim 13, in which the closing step includes the substep of closing the switch at times when the detecting step detects that the value of the supply voltage is less than the second predetermined value, the second predetermined value being the same as the first predetermined value.

Claim 20

The method of claim 13, in which the integrated circuit device further includes a third circuit capable of being activated to generate a third voltage while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the third circuit when the third circuit is activated, through the second means, and wherein the second circuit regulates in accordance with the third voltage, and wherein the method further includes the step of: deactivating the third circuit at times when the detecting step detects that the value of the supply voltage is less than the first predetermined value.

Claim 23

The method of claim 17, in which the integrated circuit device further includes a fourth circuit capable of being activated to generate a third voltage while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the fourth circuit when the fourth circuit is activated, through the second means, and wherein the second circuit regulates in accordance with the third voltage, and wherein the method further includes the step of: deactivating the fourth circuit at times when the detecting step detects that the value of the supply voltage is less than the first predetermined value.

Claim 24

A semiconductor integrated circuit device comprising: first means for receiving a supply voltage; second means for receiving a second voltage; a first circuit having a node; a second circuit capable of being activated to regulate a voltage applied to the node while conducting a first amount of current through the second means and capable of being deactivated to conduct an amount of current less than the first amount through the second means; means for deactivating the second circuit at times when the value of the supply voltage is less than a first predetermined value; and means for making an electrical connection between the first means and the node at times when the second circuit is deactivated.

Claim 25

A semiconductor integrated circuit device comprising: first means for receiving a supply voltage; second means for receiving a second voltage; a first circuit having a node; a second circuit capable of being activated to regulate a voltage applied to the node while conducting a first amount of current through the second means and capable of being deactivated to conduct an amount of current less than the first amount through the second means; means for deactivating the second circuit at times when the value of the supply voltage is less than a first predetermined value; and means for making an electrical connection between the first means and the node at times when the second circuit is deactivated.

Claim 26

The integrated circuit device of claim 19, further includes a third circuit capable of being activated to generate a third voltage while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the third circuit when the third circuit is activated, through the second means; and means for deactivating the third circuit at times when the value of the supply voltage is less than the first predetermined value, wherein the second circuit regulates in accordance with the third voltage.

Claim 27

A semiconductor integrated circuit device, adapted to receive a selection signal, comprising: first means for receiving a supply voltage; second means for receiving a second voltage; a first circuit having a node; a second circuit capable of being activated to regulate a voltage applied to the node while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the second circuit when the second circuit is activated, through the second means, the second circuit being deactivated in response to the selection signal; a third circuit capable of being activated to regulate a voltage applied to the node while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the third circuit when the third circuit is activated, through the second means; means for deactivating the second and third circuits at times when the value of the supply voltage is less than a first predetermined value; and means for making an electrical connection between the first means and the node at times when the second and third circuits are both deactivated.

Claim 28

A semiconductor integrated circuit device, adapted to receive a selection signal, comprising: first means for receiving a supply voltage; second means for receiving a second voltage; a first circuit having a node; a second circuit capable of being activated to regulate a voltage applied to the node while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the second circuit when the second circuit is activated, through the second means, the second circuit being deactivated in response to the selection signal; a third circuit capable of being activated to regulate a voltage applied to the node while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the third circuit when the third circuit is activated, through the second means; means for deactivating the second and third circuits at times when the value of the supply voltage is less than a first predetermined value; and means for making an electrical connection between the first means and the node at times when the second and third circuits are both deactivated.

Claim 29

The integrated circuit device of claim 21, further including a fourth circuit capable of being activated to generate a third voltage while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the fourth circuit when the fourth circuit is activated, through the second means, means for deactivating the fourth circuit at times when the value of the supply voltage is less than the first predetermined value, wherein the second and third circuits each regulate in accordance with the third voltage.

Claim 30

The integrated circuit device of claim 21, further including a fourth circuit capable of being activated to generate a third voltage while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the fourth circuit when the fourth circuit is activated, through the second means; a fifth circuit capable of being activated to generate a fourth voltage while conducting an amount of current through the second means and capable of being deactivated to conduct another amount of current, less than the amount conducted by the fifth circuit when the fifth circuit is activated, through the second means; and means for deactivating the fourth and fifth circuits at times when the value of the supply voltage is less than the first predetermined value, wherein the second circuit regulates in accordance with the third voltage and the third circuit regulates in accordance with the fourth voltage.