Patent US5724276A successfully refreshed from Google Patents.
US5724276A
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Logic block structure optimized for sum generation
Assignee: Xilinx Inc
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Filing: 1996-06-17
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Granted: 1998-03-03
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Expires: 2016-06-17
Abstract
Abstract The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.
Inventors
- 👤 Jonathan S. Rose
- 👤 Trevor J. Bauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:39
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5057; G06F7/501; G06F7/503; G06F7/57; G06F7/575; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4812
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
155 words
A field programmable gate array (FPGA) logic block structure comprising: a first multiplexer having at least two data inputs and at least one control input; a second multiplexer having at least two data inputs and at least one control input, said second multiplexer providing a first data input to said first multiplexer; a first lookup table having a plurality of inputs, said first lookup table providing true and complement output signals, one as a second data input to said first multiplexer and one as a first data input to said second multiplexer; a second lookup table having a plurality of inputs, said second lookup table providing a second data input to said second multiplexer; and a plurality of lines accessible from a general interconnect structure of an FPGA, one of said lines providing a control input to said first multiplexer, and other of said lines providing said inputs to said first and second lookup tables.
Claim 2
Dependent Claim
155 words
A field programmable gate array (FPGA) logic block structure comprising: a first multiplexer having at least two data inputs and at least one control input; a second multiplexer having at least two data inputs and at least one control input, said second multiplexer providing a first data input to said first multiplexer; a first lookup table having a plurality of inputs, said first lookup table providing true and complement output signals, one as a second data input to said first multiplexer and one as a first data input to said second multiplexer; a second lookup table having a plurality of inputs, said second lookup table providing a second data input to said second multiplexer; and a plurality of lines accessible from a general interconnect structure of an FPGA, one of said lines providing a control input to said first multiplexer, and other of said lines providing said inputs to said first and second lookup tables.
Claim 3
Dependent Claim
85 words
An FPGA logic block structure as in claim 1 further comprising: a carry multiplexer having at least two data inputs and at least one control input, said carry multiplexer receiving as a first data input a carry-in signal from an upstream carry multiplexer and providing a carryout signal to a location external to said logic block; one of said lines providing a second data input to said carry multiplexer, said carry multiplexer receiving as a control input one of said true and complement output signals.
Claim 4
Dependent Claim
21 words
An FPGA logic block structure as in claim 2 wherein said location external to said logic block is a downstream multiplexer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |