US5723355A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory
Assignee: CHINGIS TECHNOLOGY Corp
•
Filing: 1997-01-17
•
Granted: 1998-03-03
•
Expires: 2017-01-17
Abstract
Abstract A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.
Inventors
- 👤 Shang-De Ted Chang
- 👤 Binh Ly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:44
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/30; H10B41/35; H10B41/42; H10B41/49; H10P; H10P14/00; H10P14/40; H10P14/416; H10P76/00; H10P76/20; H10P76/204; H10P76/2041
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
288 words
A method for fabricating a memory structure having a high-voltage region, a logic region, and a memory region, where said high-voltage region comprises isolation transistors, said logic region comprises logic transistors used to perform logic operations, and said memory region comprises memory cells, said method comprising the steps of: growing a first layer of oxide on a major surface era semiconductor substrate to a thickness suitable for facilitating the tunneling of electrons therethrough; depositing a first layer of polysilicon over said first layer of oxide; removing portions of said first layer of polysilicon and said first layer of oxide which overlie said high-voltage and said logic regions, wherein the remaining portions of said first layer of polysilicon and said first layer of oxide which overlie said memory region serve as a floating gate and as a tunnel oxide, respectively, for said memory cells; growing a second layer of oxide over said memory structure; masking said second layer of oxide, using a layer of photo-resist, to expose only portions of said second layer of oxide which overlie said logic region, removing said portions of said second layer of oxide which overlie said logic region; removing said layer of photo-resist; growing a third layer of oxide over said memory structure, wherein portions of said third layer of oxide and said second layer of oxide which overlie said high-voltage region serve as gate oxides for said isolation transistors and wherein portions of said third layer of oxide and second layer of oxide which overlie said logic region serve as gate oxides for said logic transistors; and depositing and patterning a second layer of polysilicon over portions of said third layer of oxide which overlie said high-voltage region and said logic region.
Claim 2
Independent Claim
288 words
A method for fabricating a memory structure having a high-voltage region, a logic region, and a memory region, where said high-voltage region comprises isolation transistors, said logic region comprises logic transistors used to perform logic operations, and said memory region comprises memory cells, said method comprising the steps of: growing a first layer of oxide on a major surface era semiconductor substrate to a thickness suitable for facilitating the tunneling of electrons therethrough; depositing a first layer of polysilicon over said first layer of oxide; removing portions of said first layer of polysilicon and said first layer of oxide which overlie said high-voltage and said logic regions, wherein the remaining portions of said first layer of polysilicon and said first layer of oxide which overlie said memory region serve as a floating gate and as a tunnel oxide, respectively, for said memory cells; growing a second layer of oxide over said memory structure; masking said second layer of oxide, using a layer of photo-resist, to expose only portions of said second layer of oxide which overlie said logic region, removing said portions of said second layer of oxide which overlie said logic region; removing said layer of photo-resist; growing a third layer of oxide over said memory structure, wherein portions of said third layer of oxide and said second layer of oxide which overlie said high-voltage region serve as gate oxides for said isolation transistors and wherein portions of said third layer of oxide and second layer of oxide which overlie said logic region serve as gate oxides for said logic transistors; and depositing and patterning a second layer of polysilicon over portions of said third layer of oxide which overlie said high-voltage region and said logic region.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein said thickness suitable for facilitating the tunneling of electrons is approximately 80 Angstroms.
Claim 4
Dependent Claim
16 words
The method of claim 1, wherein said second layer of oxide is approximately 110 Angstroms thick.
Claim 5
Dependent Claim
18 words
The method of claim 1, wherein said gate oxides for said isolation transistors are approximately 130 Angstroms thick.
Claim 6
Dependent Claim
18 words
The method of claim 1, wherein said gate oxides for said logic transistors are approximately 65 Angstroms thick.
References Cited (Backward Citations)
US5252505A
Cited
US4651406A
Cited
US4663645A
Cited
US5061654A
Cited
US5156991A
Cited
US5057448A
Cited
US5254489A
Cited
US5580807A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |