Patent US5721882A successfully refreshed from Google Patents.
US5721882A
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Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
Assignee: Intel Corp
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Filing: 1997-02-28
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Granted: 1998-02-24
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Expires: 2017-02-28
Abstract
Abstract An apparatus which includes a state machine which tests the condition of the PCI bus, the condition of a target device on the bus, and then generates signal to accomplish the transfer which signals vary with the ability of the target device to transfer the data at particular rates.
Inventors
- 👤 Ujjwal Singh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:41
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
142 words
A computer system comprising: a main memory; a central processing unit (CPU); a first bus coupled to the CPU and to the main memory; a mezzanine bus; a first bridge circuit that separates the first bus from the mezzanine bus and provides information transfer therebetween; a bus master coupled to the mezzanine bus that controls a burst operation comprising a transfer of data on the mezzanine bus, the bus master providing signals that initiate and complete the burst operation; a bus slave coupled to the mezzanine bus that responds to the signals by asserting a ready signal which commences the transfer of data on the mezzanine bus, the bus slave including a state machine that varies a timing of the ready signal such that the transfer of data occurs synchronously on the mezzanine bus at a rate matched to the bus slave.
Claim 2
Dependent Claim
142 words
A computer system comprising: a main memory; a central processing unit (CPU); a first bus coupled to the CPU and to the main memory; a mezzanine bus; a first bridge circuit that separates the first bus from the mezzanine bus and provides information transfer therebetween; a bus master coupled to the mezzanine bus that controls a burst operation comprising a transfer of data on the mezzanine bus, the bus master providing signals that initiate and complete the burst operation; a bus slave coupled to the mezzanine bus that responds to the signals by asserting a ready signal which commences the transfer of data on the mezzanine bus, the bus slave including a state machine that varies a timing of the ready signal such that the transfer of data occurs synchronously on the mezzanine bus at a rate matched to the bus slave.
Claim 3
Dependent Claim
54 words
The computer system of claim 1 further comprising: a secondary bridge circuit; a secondary bus coupled to the mezzanine bus via the secondary bridge circuit, the mezzanine bus having a first rate of operation and the secondary bus having a second rate of operation which is substantially slower than the first rate of operation.
Claim 4
Dependent Claim
17 words
The computer system of claim 1 wherein the timing of the ready signal comprises a delay timing.
Claim 5
Dependent Claim
20 words
The computer system of claim 3 wherein the delay timing is controlled by a jumper setting of the bus slave.
Claim 6
Dependent Claim
21 words
The computer system of claim 1 wherein the state machine comprises a plurality of registers providing at least eight output states.
Claim 7
Dependent Claim
35 words
The computer system of claim 1 wherein the signals provided by the bus master include a first signal and a second signals, both of which must be asserted for the transfer of data to occur.
Claim 8
Dependent Claim
35 words
The computer system of claim 6 wherein deassertion of the second signal, while the first signal is asserted, provides an indication to the bus slave that only one transfer remains to complete the burst operation.
Claim 9
Dependent Claim
29 words
The computer system of claim 1 wherein said burst operation comprises the transfer of said data on the mezzanine bus from a sequential addresses beginning from an initial address.
Claim 10
Independent Claim
156 words
A method of synchronously transferring data in a burst operation on a mezzanine bus of a computer system which also includes a central processing unit (CPU), a CPU bus, and a secondary bus, the mezzanine bus being separated from the CPU bus by a first bridge circuit and from the secondary bus by a second bridge circuit, the method comprising the steps of: (a) providing a first signal and a second signal on the mezzanine bus by a bus master to initiate the burst operation; (b) asserting by a bus slave a ready signal on the mezzanine bus to commence the transfer of data responsive to the first and second signals, the ready signal having an associated timing; and (c) controlling the associated timing of the ready signal by a state machine of the bus slave such that the transfer of data occurs synchronously on the mezzanine bus at a rate matched to the bus slave.
Claim 11
Independent Claim
156 words
A method of synchronously transferring data in a burst operation on a mezzanine bus of a computer system which also includes a central processing unit (CPU), a CPU bus, and a secondary bus, the mezzanine bus being separated from the CPU bus by a first bridge circuit and from the secondary bus by a second bridge circuit, the method comprising the steps of: (a) providing a first signal and a second signal on the mezzanine bus by a bus master to initiate the burst operation; (b) asserting by a bus slave a ready signal on the mezzanine bus to commence the transfer of data responsive to the first and second signals, the ready signal having an associated timing; and (c) controlling the associated timing of the ready signal by a state machine of the bus slave such that the transfer of data occurs synchronously on the mezzanine bus at a rate matched to the bus slave.
Claim 12
Dependent Claim
43 words
The method according to claim 9 further comprising the step of: transitioning at least one the first signal or the second signal provided by the bus master to indicate to the bus slave that only one transfer remains to complete the burst operation.
Claim 13
Dependent Claim
17 words
The method of claim 9 wherein the associated timing of the ready signal comprises a delay timing.
Claim 14
Dependent Claim
19 words
The method of claim 11 wherein the delay timing is controlled by a jumper setting of the bus slave.
Claim 15
Dependent Claim
27 words
The method of claim 9 further comprising the step of: asserting the first signal and the second signal in order for the transfer of data to occur.
Claim 16
Dependent Claim
50 words
The method of claim 9 further comprising the step of deasserting the second signal while the first signal is asserted, wherein said deassertion of the second signal, while the first signal is asserted, provides an indication to the bus slave that only one transfer remains to complete the burst operation.
Claim 17
Dependent Claim
28 words
The method of claim 9 wherein said burst operation comprises the transfer of said data on the mezzanine bus from a sequential addresses beginning from an initial address.
Claim 18
Independent Claim
147 words
A method of synchronously transferring data in a burst operation on a mezzanine bus of a computer system which also includes a central processing unit (CPU), a CPU bus, and a secondary bus, the mezzanine bus being separated from the CPU bus by a first bridge circuit and from the secondary bus by a second bridge circuit, the method comprising the steps of: providing an initiating signal on the mezzanine bus by a bus master to initiate the burst operation; asserting by a bus slave a ready signal on the mezzanine bus to commence the transfer of data responsive to the initiating signal, the ready signal having an associated timing; and controlling the associated timing of the ready signal by a state machine of the bus slave such that the transfer of data occurs synchronously on the mezzanine bus at a rate matched to the bus slave.
Claim 19
Independent Claim
147 words
A method of synchronously transferring data in a burst operation on a mezzanine bus of a computer system which also includes a central processing unit (CPU), a CPU bus, and a secondary bus, the mezzanine bus being separated from the CPU bus by a first bridge circuit and from the secondary bus by a second bridge circuit, the method comprising the steps of: providing an initiating signal on the mezzanine bus by a bus master to initiate the burst operation; asserting by a bus slave a ready signal on the mezzanine bus to commence the transfer of data responsive to the initiating signal, the ready signal having an associated timing; and controlling the associated timing of the ready signal by a state machine of the bus slave such that the transfer of data occurs synchronously on the mezzanine bus at a rate matched to the bus slave.
Claim 20
Dependent Claim
22 words
The method of claim 16 wherein the burst operation comprises a transfer of data from sequential addresses beginning from an initial address.
Claim 21
Dependent Claim
17 words
The method of claim 16, wherein said initiating signal comprises a first signal and a second signal.
Claim 22
Dependent Claim
22 words
The method of claim 18, wherein both said first signal and said second signal are asserted for a data transfer to occur.
Claim 23
Dependent Claim
34 words
The method of claim 18 wherein when only one of said first signal and said second signal is asserted indicates to the bus slave that only one transfer remains to complete the burst operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |