US5488733A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Propulsion control system cental processing unit board
Assignee: Mercedes Benz Group AG
•
Filing: 1994-08-30
•
Granted: 1996-01-30
•
Expires: 2014-08-30
Abstract
Abstract For use in a propulsion control system, a microprocessor based central processing unit board includes both Multibus I and Multibus II interfaces. Multibus I master interface and Multibus slave interface controllers are designed for high data throughput by using programmed logic design (PLD) technology. In addition, the need for latching of data transceivers used in conventional Multibus I designs is eliminated. The Multibus II interface is removable.
Inventors
- 👤 William F. Molyneaux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:34
CPC Classifications
B; B60; B60L; B60L9/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
344 words
A propulsion control system for controlling a vehicle, said propulsion control system comprising: a field connector interface board connected to vehicle wiring; a plurality of master and slave interface and control boards connected to the field connector interface board, said plurality of master and slave interface and control boards including a digital input-output board, an analog input-output board, a bitbus board, a tach reader board, a memory board, and a master CPU board, each of which are connected to the field connector interface board; a first bus connected to the plurality of master and slave interface and control boards and a second bus connected to the master CPU board; wherein, the master CPU board comprises: a local bus; memory; a multifunction peripheral device; and a central processing unit operatively connected to said memory and said multifunction peripheral device by said local bus, with said multifunction peripheral device including: wait state generator means for generating timing signals, direct memory access control means for controlling data transfer in said system, and interrupt handling means for generating interrupt requests and handling direct memory access interrupts; a first bus interface, operatively connected to said multifunction peripheral device and said local bus, including: first bus master control logic means for controlling the first bus responsive to said interrupt requests from said interrupt handling means; and buffering means for buffering data between said local bus and the first bus responsive to said first bus control logic means; and a second bus interface, operatively connected to said multifunction peripheral device, including: second bus master control logic means for controlling the second bus and producing said direct memory access interrupts; interconnect means for interfacing control signals from said second bus control logic means; reset control having an output connected to said interconnect means; and buffering means for buffering data between the second bus and said second bus control logic means responsive to control signals from said interconnect means; with said central processing unit circuit board communicating with the remaining components of said propulsion control system via said first and said second buses.
Claim 2
Dependent Claim
344 words
A propulsion control system for controlling a vehicle, said propulsion control system comprising: a field connector interface board connected to vehicle wiring; a plurality of master and slave interface and control boards connected to the field connector interface board, said plurality of master and slave interface and control boards including a digital input-output board, an analog input-output board, a bitbus board, a tach reader board, a memory board, and a master CPU board, each of which are connected to the field connector interface board; a first bus connected to the plurality of master and slave interface and control boards and a second bus connected to the master CPU board; wherein, the master CPU board comprises: a local bus; memory; a multifunction peripheral device; and a central processing unit operatively connected to said memory and said multifunction peripheral device by said local bus, with said multifunction peripheral device including: wait state generator means for generating timing signals, direct memory access control means for controlling data transfer in said system, and interrupt handling means for generating interrupt requests and handling direct memory access interrupts; a first bus interface, operatively connected to said multifunction peripheral device and said local bus, including: first bus master control logic means for controlling the first bus responsive to said interrupt requests from said interrupt handling means; and buffering means for buffering data between said local bus and the first bus responsive to said first bus control logic means; and a second bus interface, operatively connected to said multifunction peripheral device, including: second bus master control logic means for controlling the second bus and producing said direct memory access interrupts; interconnect means for interfacing control signals from said second bus control logic means; reset control having an output connected to said interconnect means; and buffering means for buffering data between the second bus and said second bus control logic means responsive to control signals from said interconnect means; with said central processing unit circuit board communicating with the remaining components of said propulsion control system via said first and said second buses.
Claim 3
Dependent Claim
105 words
The propulsion control system according to claim 1, wherein said first bus master control logic means for controlling the first bus comprises: bus control logic means for producing timing and control signals; arbiter means, responsive to said timing and control signals, for providing bus protocol control and synchronization of the central processor with the first bus; decoder means, responsive to said timing and control signals, for enabling said bus control logic means responsive to address signals from the central processor; and latch control means, responsive to said timing and control signals, for generating command and control timing for the first bus to optimize its performance.
References Cited (Backward Citations)
US4626843A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |