US5716890A
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US
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Structure and method for fabricating an interlayer insulating film
Assignee: Vanguard International Semiconductor Corp
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Filing: 1996-10-18
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Granted: 1998-02-10
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Expires: 2016-10-18
Abstract
Abstract The present invention provides a structure and method of manufacturing an interlevel/intermetal dielectric layer for a semiconductor device. The method begins by forming a stepped pattern 16 on a semiconductor structure 12. A barrier layer 20 composed of silicon oxide is formed on the semiconductor substrate so as to cover the surface of the stepped pattern 16. A first insulating layer 22 composed of silicon oxide is then formed over the barrier layer 20. A high P (phosphorous) content silicon glass layer 24 preferably is formed over the first insulating layer 22. The high P content silicon glass layer 24 has a phosphorous concentration in a range of about 4 and 10 weight percent. Next, in an important step, a graded P content silicon glass layer 26 is formed over the high P content silicon glass layer 24. The graded P content silicon glass layer 26 has a phosphorous concentration in a range of about 0.1 and 4 weight percent. A capping layer 28 composed of first silicon oxide is formed over the graded P content silicon glass layer 26. The capping layer can be treated with an optional N2 or Ar plasma treatment. The capping layer 28 is then planarized using a chemical mechanically polishing process thereby removing a portion of the capping layer 28.
Inventors
- 👤 Liang-Gi Yao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:41
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/65; H10P14/6502; H10P14/6506; H10P14/6516; H10P14/6548; H10P14/66; H10P14/662; H10P14/69215; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/077; H10W20/093; H10W20/096; H10W20/40; H10W20/45; H10W20/47; H10W20/48
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
199 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) forming a barrier layer on said semiconductor structure and covering the surface of said stepped pattern; c) forming a first insulating layer composed of silicon oxide over said barrier layer; d) forming a high phosphorous content silicon glass layer over said first insulating layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; e) forming an graded P content silicon glass layer over said first high P content silicon glass layer; said graded P content silicon glass layer having a top and a bottom; said bottom adjacent to said high phosphorous content silicon glass layer; said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top; said graded P content silicon glass layer formed by adjusting a gas flow of a P containing gas during the formation of said graded P content silicon glass layer; and f) forming a capping layer composed of a silicon oxide on said graded P content silicon glass layer.
Claim 2
Independent Claim
199 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) forming a barrier layer on said semiconductor structure and covering the surface of said stepped pattern; c) forming a first insulating layer composed of silicon oxide over said barrier layer; d) forming a high phosphorous content silicon glass layer over said first insulating layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; e) forming an graded P content silicon glass layer over said first high P content silicon glass layer; said graded P content silicon glass layer having a top and a bottom; said bottom adjacent to said high phosphorous content silicon glass layer; said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top; said graded P content silicon glass layer formed by adjusting a gas flow of a P containing gas during the formation of said graded P content silicon glass layer; and f) forming a capping layer composed of a silicon oxide on said graded P content silicon glass layer.
Claim 3
Dependent Claim
34 words
The method of claim 1 which further includes treating said capping layer with a plasma treatment; said plasma treatment using a gas of a material selected from the group consisting of: Nitrogen and argon.
Claim 4
Dependent Claim
63 words
The method of claim 1 which further includes treating said capping layer with a plasma treatment; said plasma treatment using a gas of a material selected from the group consisting of: Nitrogen and argon; and planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 2000 and 12,000 Å.
Claim 5
Dependent Claim
104 words
The method of claim 1 which further includes treating said capping layer with a plasma treatment; said plasma treatment using a gas of a material selected from the group consisting of nitrogen and argon; and planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 2000 and 11,000 Å resulting in the total thickness of said barrier layer, said first insulation layer, said high P content silicon glass layer, said graded P content silicon glass layer and said capping layer is in a range of about 8000 and 22,000 Å.
Claim 6
Dependent Claim
44 words
The method of claim 1 wherein said step pattern has a height above said semiconductor structure in a range of about 5000 and 10,000 Å and said gaps have a width between said step pattern in a range of about 0.3 and 0.8 μm.
Claim 7
Dependent Claim
39 words
The method of claim 1 wherein said barrier layer is composed of a material selected from the group consisting of silicon oxide, silicon nitride, and oxynitride, having a thickness in a range of between about 500 and 2000 Å.
Claim 8
Dependent Claim
33 words
The method of claim 1 wherein said first insulating layer is composed of silicon oxide, and said first insulating layer having a thickness in a range of between about 4000 and 10,000 Å.
Claim 9
Dependent Claim
26 words
The method of claim 1 wherein said high P content silicon glass layer has a thickness in a range of between about 3000 and 7000 Å.
Claim 10
Dependent Claim
40 words
The method of claim 1 wherein said graded P content silicon glass layer has a phosphorous concentration in a range of about 0.1 and 4 weight percent and a thickness in a range of between about 200 and 2000 Å.
Claim 11
Dependent Claim
25 words
The method of claim 1 wherein said capping layer is made by a process selected from the group consisting of an ozone -TEOS and PECVD.
Claim 12
Dependent Claim
34 words
The method of claim 1 wherein said graded P content silicon glass layer has a P concentration of 0.1 wt % near said top and a P concentration of about 4% near said bottom.
Claim 13
Dependent Claim
53 words
The method of claim 1 wherein said graded P content silicon glass layer has a P concentration of 0.1 wt % near said top and a P concentration of about 4% near said bottom; said P concentration decreases linearly throughout said graded P content silicon glass layer from said bottom to said top.
Claim 14
Dependent Claim
60 words
The method of claim 1 wherein said graded P content silicon glass layer has a P concentration of 0.1 wt % at said top and a P concentration of about 4% at said bottom; said P concentration decreases linearly throughout said graded P content silicon glass layer from said bottom to said top; and said P containing gas comprises TEPO.
Claim 15
Independent Claim
273 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) forming a barrier layer composed of silicon oxide on said semiconductor structure and coveting the surface of said stepped pattern; said barrier layer having a thickness in a range of between about 500 and 2000 Å, said barrier layer formed by a process selected from the group consisting of: plasma enhanced chemical vapor deposition, LPCVD, and ozone - TEOS; c) forming a first insulating layer composed of silicon oxide over said barrier layer, and said first, insulating layer having a thickness in a range of between about 3000 and 8000 Å; d) forming a high phosphorous content silicon glass layer over said first insulating layer, said high P content silicon glass layer having a phosphorous concentration in a range of about 4 and 10 weight percent, a thickness in a range of between about 3000 and 7000 Å; e) forming a graded P content silicon glass layer over said first high P content silicon glass layer, said graded P content silicon glass layer having a phosphorous concentration in a range of about 0.1 and 4 weight percent and a thickness in a range of between about 200 and 2000 Å. f) forming a capping layer composed of first silicon oxide over said graded P content silicon glass layer, g) treating said capping layer with a plasma treatment; h) planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 4000 and 12,000 Å.
Claim 16
Independent Claim
273 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) forming a barrier layer composed of silicon oxide on said semiconductor structure and coveting the surface of said stepped pattern; said barrier layer having a thickness in a range of between about 500 and 2000 Å, said barrier layer formed by a process selected from the group consisting of: plasma enhanced chemical vapor deposition, LPCVD, and ozone - TEOS; c) forming a first insulating layer composed of silicon oxide over said barrier layer, and said first, insulating layer having a thickness in a range of between about 3000 and 8000 Å; d) forming a high phosphorous content silicon glass layer over said first insulating layer, said high P content silicon glass layer having a phosphorous concentration in a range of about 4 and 10 weight percent, a thickness in a range of between about 3000 and 7000 Å; e) forming a graded P content silicon glass layer over said first high P content silicon glass layer, said graded P content silicon glass layer having a phosphorous concentration in a range of about 0.1 and 4 weight percent and a thickness in a range of between about 200 and 2000 Å. f) forming a capping layer composed of first silicon oxide over said graded P content silicon glass layer, g) treating said capping layer with a plasma treatment; h) planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 4000 and 12,000 Å.
Claim 17
Dependent Claim
44 words
The method of claim 14 wherein said step pattern has a height above said semiconductor structure in a range of about 5000 and 10,000 Å and said gaps have a width between said step pattern in a range of about 0.3 and 0.8 μm.
Claim 18
Dependent Claim
48 words
The method of claim 14 wherein after step (h) the total thickness of said barrier layer, said first insulation layer, said high P content silicon glass layer, said graded P content silicon glass layer and said capping layer is in a range of about 4000 and 12,000 Å.
Claim 19
Independent Claim
255 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure; said stepped pattern having gaps therebetween; b) forming a barrier layer composed of silicon oxide over said semiconductor structure and said stepped pattern; said barrier layer having a thickness in a range of between about 500 and 2000 Å; said barrier layer formed by a process selected from the group consisting of: PECVD, LPCVD and ozone-TEOS; c) forming a high phosphorous content silicon glass layer over said barrier layer, said high P content silicon glass layer having a phosphorous concentration in a range of about 4 and 10 weight percent; a thickness in a range of between about 3000 and 7000 Å; d) forming a graded P content silicon glass layer over said high P (phosphorous) content silicon glass layer, said graded P content silicon glass layer having a phosphorous concentration in a range of about 0.1 and 4 weight percent and a thickness in a range of between about 200 and 2000 Å; e) forming a capping layer composed of silicon oxide over said graded P content silicon glass layer; said capping layer formed by PE-TEOS process, of said capping layer having a thickness in a range of between about 4000 and 12,000 Å; f) treating said first silicon oxide layer with a plasma treatment; g) planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 2000 and 8000 Å.
Claim 20
Independent Claim
255 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure; said stepped pattern having gaps therebetween; b) forming a barrier layer composed of silicon oxide over said semiconductor structure and said stepped pattern; said barrier layer having a thickness in a range of between about 500 and 2000 Å; said barrier layer formed by a process selected from the group consisting of: PECVD, LPCVD and ozone-TEOS; c) forming a high phosphorous content silicon glass layer over said barrier layer, said high P content silicon glass layer having a phosphorous concentration in a range of about 4 and 10 weight percent; a thickness in a range of between about 3000 and 7000 Å; d) forming a graded P content silicon glass layer over said high P (phosphorous) content silicon glass layer, said graded P content silicon glass layer having a phosphorous concentration in a range of about 0.1 and 4 weight percent and a thickness in a range of between about 200 and 2000 Å; e) forming a capping layer composed of silicon oxide over said graded P content silicon glass layer; said capping layer formed by PE-TEOS process, of said capping layer having a thickness in a range of between about 4000 and 12,000 Å; f) treating said first silicon oxide layer with a plasma treatment; g) planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 2000 and 8000 Å.
Claim 21
Dependent Claim
44 words
The method of claim 17 wherein said step pattern has a height above said semiconductor structure in a range of about 5000 and 10,000 Å and said gaps have a width between said step pattern in a range of about 0.5 and 1.0 μm.
Claim 22
Dependent Claim
47 words
The method of claim 17 wherein after step (g) the total thickness of said barrier layer, said high P content silicon glass layer, said graded P content silicon glass layer and said second silicon oxide layer is in a range of between about 8000 and 22,000 Å.
Claim 23
Dependent Claim
161 words
An interlayer insulating layer for a semiconductor device, comprising: a) a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) a barrier layer on said semiconductor structure covering the surface of said stepped pattern; c) a first insulating layer composed of silicon oxide over said barrier layer; d) a high phosphorous content silicon glass layer over said first insulating layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; e) a graded P content silicon glass layer over said first high P content silicon glass layer; said graded P content silicon glass layer having a top and a bottom; said bottom adjacent to said high phosphorous content silicon glass layer; said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top; and f) a capping layer composed of first silicon oxide over said graded P content silicon glass layer.
Claim 24
Dependent Claim
161 words
An interlayer insulating layer for a semiconductor device, comprising: a) a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) a barrier layer on said semiconductor structure covering the surface of said stepped pattern; c) a first insulating layer composed of silicon oxide over said barrier layer; d) a high phosphorous content silicon glass layer over said first insulating layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; e) a graded P content silicon glass layer over said first high P content silicon glass layer; said graded P content silicon glass layer having a top and a bottom; said bottom adjacent to said high phosphorous content silicon glass layer; said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top; and f) a capping layer composed of first silicon oxide over said graded P content silicon glass layer.
Claim 25
Dependent Claim
64 words
The interlayer insulating layer of claim 20 wherein said capping layer has a thickness in a range of between about 2000 and 11,000 Å, the total thickness of said barrier layer, said first insulation layer, said high P content silicon glass layer, said graded P content silicon glass layer and said capping layer is in a range of about between 8000 and 22,000 Å.
Claim 26
Dependent Claim
47 words
The interlayer insulating layer of claim 20 wherein said step pattern has a height above said semiconductor structure in a range of about 5000 and 10,000 Å and said gaps have a width between said step pattern in a range of between about 0.3 and 0.8 μm.
Claim 27
Dependent Claim
41 words
The interlayer insulating layer of claim 20 wherein said barrier layer is composed of a material selected from the group consisting of silicon oxide, silicon nitride, and oxynitride, having a thickness in a range of between about 500 and 2000 Å.
Claim 28
Dependent Claim
35 words
The interlayer insulating layer of claim 20 wherein said first insulating layer is composed of silicon oxide, and said first insulating layer has a thickness in a range of between about 4000 and 10,000 Å.
Claim 29
Dependent Claim
28 words
The interlayer insulating layer of claim 20 wherein said high P content silicon glass layer having a thickness in a range of between about 3000 and 7000 Å.
Claim 30
Dependent Claim
42 words
The interlayer insulating layer of claim 20 wherein said graded P content silicon glass layer has a phosphorous concentration in a range of about 0.1 and 4 weight percent and a thickness in a range of between about 200 and 2000 Å.
Claim 31
Dependent Claim
58 words
The interlayer insulating layer of claim 20 wherein said graded P content silicon glass layer has a P concentration of 0.1 wt % near said top and a P concentration of about 4% near said bottom; and said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top.
Claim 32
Dependent Claim
55 words
The interlayer insulating layer of claim 20 wherein said graded P content silicon glass layer has a P concentration of 0.1 wt % near said top and a P concentration of about 4% near said bottom; said P concentration decreases linearly throughout said graded P content silicon glass layer from said bottom to said top.
Claim 33
Dependent Claim
147 words
An interlayer insulating layer for a semiconductor device, comprising: a) a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) a barrier layer on said semiconductor structure coveting the surface of said stepped pattern; c) a high phosphorous content silicon glass layer over said barrier layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; d) a graded P content silicon glass layer over said first high P content silicon glass layer; said graded P content silicon glass layer having a top and a bottom; said bottom adjacent to said high phosphorous content silicon glass layer; said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top; and e) a capping layer composed of first silicon oxide over said graded P content silicon glass layer.
Claim 34
Dependent Claim
147 words
An interlayer insulating layer for a semiconductor device, comprising: a) a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) a barrier layer on said semiconductor structure coveting the surface of said stepped pattern; c) a high phosphorous content silicon glass layer over said barrier layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; d) a graded P content silicon glass layer over said first high P content silicon glass layer; said graded P content silicon glass layer having a top and a bottom; said bottom adjacent to said high phosphorous content silicon glass layer; said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top; and e) a capping layer composed of first silicon oxide over said graded P content silicon glass layer.
Claim 35
Dependent Claim
55 words
The interlayer insulating layer of claim 29 wherein said step pattern has a height above said semiconductor structure in a range of about 5000 and 10,000 Å and said gaps have a width between said step pattern in a range of between about 0.5 and 1.0 μm, and said stepped pattern is a gate electrode.
Claim 36
Dependent Claim
41 words
The interlayer insulating layer of claim 29 wherein said barrier layer is composed of a material selected from the group consisting of silicon oxide, silicon nitride, and oxynitride, having a thickness in a range of between about 500 and 2000 Å.
Claim 37
Dependent Claim
28 words
The interlayer insulating layer of claim 29 wherein said high V content silicon glass layer has a thickness in a range of between about 3000 and 7000 Å.
Claim 38
Dependent Claim
42 words
The interlayer insulating layer of claim 29 wherein said graded P content silicon glass layer has a phosphorous concentration in a range of about 0.1 and 4 weight percent and a thickness in a range of between about 200 and 2000 Å.
Claim 39
Dependent Claim
58 words
The interlayer insulating layer of claim 29 wherein said graded P content silicon glass layer has a P concentration of 0.1 wt % near said top and a P concentration of about 4% near said bottom; and said P concentration decreasing throughout the thickness of said graded P content silicon glass layer from said bottom to said top.
Claim 40
Dependent Claim
55 words
The interlayer insulating layer of claim 29 wherein said graded P content silicon glass layer has a P concentration of 0.1 wt % at said top and a P concentration of about 4% at said bottom; said P concentration decreases linearly throughout said graded P content silicon glass layer from said bottom to said top.
Claim 41
Independent Claim
181 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) forming a barrier layer on said semiconductor structure and covering the surface of said stepped pattern; c) forming a first insulating layer composed of silicon oxide over said barrier layer; d) forming a high phosphorous content silicon glass layer over said first insulating layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; e) forming a graded P content silicon glass layer over said first high P content silicon glass layer; and f) forming a capping layer composed of a silicon oxide over said graded P content silicon glass layer; treating said capping layer with a plasma treatment; said plasma treatment using a gas of a material selected from the group consisting of: Nitrogen and argon; and h) planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 2000 and 12,000 Å.
Claim 42
Independent Claim
181 words
A method of manufacturing a semiconductor device, comprising the steps of: a) forming a stepped pattern on a semiconductor structure, said stepped pattern having gaps therebetween; b) forming a barrier layer on said semiconductor structure and covering the surface of said stepped pattern; c) forming a first insulating layer composed of silicon oxide over said barrier layer; d) forming a high phosphorous content silicon glass layer over said first insulating layer; said high phosphorous content silicon glass layer having a phosphorous content between 4 and 10 weight %; e) forming a graded P content silicon glass layer over said first high P content silicon glass layer; and f) forming a capping layer composed of a silicon oxide over said graded P content silicon glass layer; treating said capping layer with a plasma treatment; said plasma treatment using a gas of a material selected from the group consisting of: Nitrogen and argon; and h) planarizing said capping layer using a chemical mechanically polishing process thereby removing a thickness of said capping layer in a range of between about 2000 and 12,000 Å.
Claim 43
Dependent Claim
47 words
The method of claim 36 which further includes: the total thickness of said barrier layer, said first insulation layer, said high P content silicon glass layer, said graded P content silicon glass layer and said capping layer is in a range of about 8000 and 22,000 Å.
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