Patent US5710450A successfully refreshed from Google Patents.
US5710450A
Expired / Lapsed
US
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Transistor with ultra shallow tip and method of fabrication
Assignee: Intel Corp
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Filing: 1994-12-23
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Granted: 1998-01-20
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Expires: 2014-12-23
Abstract
Abstract A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.
Inventors
- 👤 Robert S. Chau
- 👤 Chan-Hong Chern
- 👤 Chia-Hong Jan
- 👤 Kevin R. Weldon
- 👤 Paul A. Packan
- 👤 Leopoldo D. Yau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:41
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D30/0227; H10D30/027; H10D30/0275; H10D30/60; H10D30/601; H10D30/608; H10D62/01; H10D62/021; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01314; H10D64/021; H10D64/025; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0172; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
91 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a first surface of semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a first pair of sidewall spacers adjacent to opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate beneath said first surface and in alignment with the outside edges of said first pair of sidewall spacers; and forming a first semiconductor material in said pair of recesses to form a pair of source/drain regions.
Claim 2
Independent Claim
91 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a first surface of semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a first pair of sidewall spacers adjacent to opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate beneath said first surface and in alignment with the outside edges of said first pair of sidewall spacers; and forming a first semiconductor material in said pair of recesses to form a pair of source/drain regions.
Claim 3
Dependent Claim
28 words
The method of claim 1 further comprising the step of: diffusing dopants from said first semiconductor material into said substrate beneath said first pair of said sidewall spacers.
Claim 4
Dependent Claim
34 words
The method of claim 2 further comprising the step of: forming a second pair of sidewall spacers on said first semiconductor material adjacent to the outside edges of said first pair of sidewall spacers.
Claim 5
Dependent Claim
33 words
The method of claim 3 further comprising the step of: depositing ions into said first semiconductor material and said substrate in alignment with the outside edges of said second pair of sidewall spacers.
Claim 6
Dependent Claim
13 words
The method of claim 4 wherein said ions are deposited by ion implantation.
Claim 7
Dependent Claim
29 words
The method of claim 3 further comprising the step of: forming silicide on said semiconductor material in alignment with the outside edges of said second pair of sidewall spacers.
Claim 8
Dependent Claim
33 words
The method of claim 3 further comprising the step of: forming a second semiconductor material on said first semiconductor material in alignment with the outside edges of said second pair of sidewall spacers.
Claim 9
Dependent Claim
17 words
The method of claim 7 further comprising the step of: forming silicide on said second semiconductor material.
Claim 10
Independent Claim
140 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a first pair of sidewall spacers adjacent to opposite sides of said gate electrode; forming a first doped semiconductor material on said semiconductor substrate in alignment with the outside edges of said first sidewall spacers; diffusing dopants from said first semiconductor material into said substrate beneath said first pair of sidewall spacers to form a pair of tip regions; forming a second pair of sidewall spacers on said first semiconductor material adjacent to the outside edges of said first pair of sidewall spacers; and implanting ions into said semiconductor material and said substrate in alignment with the outside edges of said second pair of sidewall spacers to form source/drain contact regions.
Claim 11
Independent Claim
140 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a first pair of sidewall spacers adjacent to opposite sides of said gate electrode; forming a first doped semiconductor material on said semiconductor substrate in alignment with the outside edges of said first sidewall spacers; diffusing dopants from said first semiconductor material into said substrate beneath said first pair of sidewall spacers to form a pair of tip regions; forming a second pair of sidewall spacers on said first semiconductor material adjacent to the outside edges of said first pair of sidewall spacers; and implanting ions into said semiconductor material and said substrate in alignment with the outside edges of said second pair of sidewall spacers to form source/drain contact regions.
Claim 12
Dependent Claim
16 words
The method of claim 9 wherein said first pair of spacers are between 50 Å-500 Å.
Claim 13
Dependent Claim
14 words
The method of claim 9 wherein said ion implantation step dopes said gate electrode.
Claim 14
Dependent Claim
30 words
The method of claim 9 further comprising the step of: forming silicide on said first semiconductor material in alignment with the outside edges of said second pair of sidewall spacers.
Claim 15
Dependent Claim
34 words
The method of claim 9 further comprising the step of: forming a second semiconductor material on said first said semiconductor material in alignment with the outside edges of said second pair of sidewall spacers.
Claim 16
Dependent Claim
17 words
The method of claim 13 further comprising the step of: forming silicide on said second semiconductor material.
Claim 17
Dependent Claim
123 words
A transistor comprising: a gate dielectric layer formed on said first surface of a semiconductor substrate; a gate electrode formed on said gate dielectric layer; a first pair of sidewall spacers adjacent to and on opposite sides of said gate electrode; a first pair of ultra shallow tip regions formed in said, semiconductor substrate and extending beneath said first pair of sidewall spacers and opposite sides of said gate electrode; a pair of raised tip regions formed in alignment with the outside edges of said first pair of said sidewall spacers wherein said pair of raised tip regions comprise a first deposited semiconductor material with the least a portion of said semiconductor material above and below said first surface of said semiconductor substrate.
Claim 18
Dependent Claim
123 words
A transistor comprising: a gate dielectric layer formed on said first surface of a semiconductor substrate; a gate electrode formed on said gate dielectric layer; a first pair of sidewall spacers adjacent to and on opposite sides of said gate electrode; a first pair of ultra shallow tip regions formed in said, semiconductor substrate and extending beneath said first pair of sidewall spacers and opposite sides of said gate electrode; a pair of raised tip regions formed in alignment with the outside edges of said first pair of said sidewall spacers wherein said pair of raised tip regions comprise a first deposited semiconductor material with the least a portion of said semiconductor material above and below said first surface of said semiconductor substrate.
Claim 19
Dependent Claim
39 words
The transistor of claim 15 further comprising: a second pair of sidewall spacers formed adjacent to the outside edges of said first pair of spacers, said second pair of sidewall spacers formed on said pair of raised tip regions.
Claim 20
Dependent Claim
41 words
The transistor of claim 15 further comprising: a pair of source/drain contact regions formed in alignment with said second pair of sidewall spacers, said pair of source/drain contact regions formed deeper into said substrate than said pair of raised tip regions.
Claim 21
Dependent Claim
21 words
The transistor of claim 16 further comprising silicide formed on said pair of source/drain contact regions and on said gate electrode.
Claim 22
Dependent Claim
29 words
The transistor of claim 16 further comprising a second semiconductor material formed on said first deposited semiconductor material adjacent to the outside edges of said second pair of spacers.
Claim 23
Dependent Claim
14 words
The transistor of claim 19 further comprising silicide formed on said second semiconductor material.
Claim 24
Dependent Claim
15 words
The transistor of claim 15 wherein said pair of raised tip regions comprise deposited polysilicon.
Claim 25
Dependent Claim
17 words
The transistor of claim 15 wherein said pair of raised tip regions comprise deposited single crystalline silicon.
Claim 26
Dependent Claim
16 words
The transistor of claim 15 wherein said pair of raised tip regions comprise deposited silicon/germanium semiconductor.
Claim 27
Dependent Claim
19 words
The transistor of claim 15 wherein said first pair of sidewall spacers are between approximately 50 Å-500 Å thick.
Claim 28
Dependent Claim
19 words
The transistor of claim 15 wherein said second pair of sidewall spacers are between approximately 500 Å-2500 Å thick.
Claim 29
Dependent Claim
26 words
The transistor of claim 15 wherein said pair of raised tip regions extend between approximately 20 Å-1000 Å beneath said first surface of said semiconductor substrate.
Claim 30
Dependent Claim
36 words
The transistor of claim 15 wherein said pair of ultra shallow tip regions have a depth between 20 Å-100 Å beneath said first surface of said semiconductor substrate and a length of greater than 100 Å.
Claim 31
Independent Claim
57 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a first surface of a semiconductor substrate; forming a gate electrode on said gate dielectric layer: forming a pair of recesses in semiconductor substrate on opposite sides of said gate electrode; and forming a pair of source/drain regions through said recesses.
Claim 32
Independent Claim
57 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a first surface of a semiconductor substrate; forming a gate electrode on said gate dielectric layer: forming a pair of recesses in semiconductor substrate on opposite sides of said gate electrode; and forming a pair of source/drain regions through said recesses.
Claim 33
Independent Claim
75 words
A method of forming a transistor comprising the steps of: forming a gate electrode on a gate dielectric layer on a first surface of a semiconductor substrate; forming a pair of sidewall spacers adjacent to opposite side of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edge of said first pair of sidewall spacers; and forming a pair of source/drain regions through said pair of recesses.
Claim 34
Independent Claim
75 words
A method of forming a transistor comprising the steps of: forming a gate electrode on a gate dielectric layer on a first surface of a semiconductor substrate; forming a pair of sidewall spacers adjacent to opposite side of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edge of said first pair of sidewall spacers; and forming a pair of source/drain regions through said pair of recesses.
Claim 35
Independent Claim
51 words
A method of forming a transistor comprising the steps of: forming a gate electrode on a gate dielectric layer of a semiconductor substrate; forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode; and forming a pair of source/drain regions in said pair of recesses.
Claim 36
Independent Claim
51 words
A method of forming a transistor comprising the steps of: forming a gate electrode on a gate dielectric layer of a semiconductor substrate; forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode; and forming a pair of source/drain regions in said pair of recesses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-19 | 2001-07-21 | 2002-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-19 | 2005-07-21 | 2006-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-19 | 2009-07-21 | 2010-01-20 | $7700.00 | Window Closed / Lapsed |