CMOS output buffer with reduced L-DI/DT noise

Claim 2

An output buffer comprising: a terminal, a first driver for driving said terminal to a voltage corresponding to a logic value of a to-be-outputted signal, a second driver for driving said terminal to said same voltage as said first driver, when said to-be-outputted signal transitions in logic value, and enable circuitry, having at least one input, said enable circuitry responds to a transition in logic value of said to-be-outputted signal by, after a predetermined delay following a time at which said first driver begins to drive said terminal, enabling said second driver to drive said terminal, but only enabling said second driver to drive said terminal for a predetermined time period, each input of said enable circuitry receiving the same signal as a corresponding input of said first driver.

Claim 3

The output buffer of claim 1, wherein said enable circuitry comprises: at least one delay element, which receives said to-be-outputted signal and which outputs at least one delayed output signal, after said predetermined delay, and a memory, which responds to said at least one delayed output signal outputted by said at least one delay element, by outputting at least on previously stored enabling value, for said predetermined time period, and by outputting at least one newly stored disabling value thereafter, said at least one previously stored enabling value enabling said second driver to drive said terminal and said at least one newly stored disabling value preventing said second driver from driving said terminal.

Claim 4

The output buffer of claim 2 wherein said enable circuitry further comprises: logic circuitry which responds to said at least one delayed output signal and said at least one previously stored enabling value by enabling said second driver to drive said terminal to a first voltage, when said to-be-outputted signal transitions to a first logic value corresponding to said first voltage, and for enabling said second driver to output a second voltage, when said to-be-outputted signal transitions to a second logic value corresponding to said second voltage.

Claim 5

The output buffer of claim 2 wherein said memory comprises: a first logic gate, receiving as a first input, at least one of said at least one delayed output signals from at least one of said at least one delay elements, a second logic gate, receiving as a first input, at least one of said at least one delayed output signals from at least one of said at least one delay elements, a second delay element connected between an output of said first logic gate and a second input of said second logic gate, and a third delay element connected between an output of said second logic gate and a second input of said first logic gate.

Claim 6

The output buffer of claim 1 further comprising: a predriver circuit which receives said to-be-outputted signal and enables said first driver to drive said terminal to a first voltage when said to-be-outputted signal is a first logic value corresponding to said first voltage and for enabling said first driver to drive said terminal to a second voltage when said to-be-outputted signal is a second logic value corresponding to a second voltage.

Claim 7

The output buffer of claim 5 wherein said first driver comprises: a first transistor having an output connected to said terminal, for driving said terminal to said first voltage, and a second transistor having an output connected to said terminal, for driving said terminal to said second voltage, wherein said predriver comprises a first inverter, receiving said to-be-outputted signal at its input and outputting a complement of said to-be-outputted signal to an input of said first transistor, and a second inverter, receiving said to-be-outputted signal at its first input and outputting a complement of said to-be-outputted signal to an input of said second transistor.

Claim 8

The output buffer of claim 6 wherein said first and second inverters each comprise third and fourth transistors, which each have an input and output, said third transistor input being connected to said fourth transistor input and said third transistor output being connected to said fourth transistor output, said third transistor for outputting said first voltage, when said to-be-outputted signal is said second logic value and said fourth transistor for outputting said second voltage, when said to-be-outputted signal is said first logic value, wherein sizes of said third and fourth transistors of said first and second inverters are selected so that, in response to said to-be-outputted signal transitioning from said second logic value to said first logic value, said fourth transistor of said first inverter enables said first transistor more slowly than said fourth transistor of said second inverter disables said second transistor, and so that, in response to said to-be-outputted signal transitioning from said first logic value to said second logic value, said third transistor of said second inverter enables said second transistor more slowly than said third transistor of said first inverter disables said first transistor.

Claim 9

Enable circuitry having at least one input for enabling a transient driver, that assists a steady state driver in driving a terminal to a first voltage corresponding to a first logic value of a to-be-outputted signal or a second voltage corresponding to a second logic value of said to-be-outputted signal comprising: a first delay element, for delaying said to-be-outputted signal by a predetermined period of time following a time at which said steady state driver beings to drive said terminal, a first circuit, receiving said delayed to-be-outputted signal that is outputted from said first delay element, and responding, after said predetermined delay, to a transition in logic value in said delayed to-be-outputted signal by outputting one or more enable signals that enable said transient driver to output logic said first voltage in response to said delayed to-be-outputted signal transitioning from said second logic value to said first logic value and to output said second voltage in response to said delayed to-be-outputted signal transitioning from said first logic value to said second logic value, said first circuit comprising an internal feedback path with a second delay element, having a second predetermined delay, for limiting a time period, during which said first circuit generates said one or more enable signals, to said second predetermined delay, so as to limit a time, during which said transient driver is enabled to drive said terminal to said first or second voltage, to said second predetermined delay wherein each input of said enable circuitry receives the same signals as a corresponding input of said steady state driver.

Claim 10

Enable circuitry having at least one input for enabling a transient driver, that assists a steady state driver in driving a terminal to a first voltage corresponding to a first logic value of a to-be-outputted signal or a second voltage corresponding to a second logic value of said to-be-outputted signal comprising: a first delay element, for delaying said to-be-outputted signal by a predetermined period of time following a time at which said steady state driver beings to drive said terminal, a first circuit, receiving said delayed to-be-outputted signal that is outputted from said first delay element, and responding, after said predetermined delay, to a transition in logic value in said delayed to-be-outputted signal by outputting one or more enable signals that enable said transient driver to output logic said first voltage in response to said delayed to-be-outputted signal transitioning from said second logic value to said first logic value and to output said second voltage in response to said delayed to-be-outputted signal transitioning from said first logic value to said second logic value, said first circuit comprising an internal feedback path with a second delay element, having a second predetermined delay, for limiting a time period, during which said first circuit generates said one or more enable signals, to said second predetermined delay, so as to limit a time, during which said transient driver is enabled to drive said terminal to said first or second voltage, to said second predetermined delay wherein each input of said enable circuitry receives the same signals as a corresponding input of said steady state driver.

Claim 11

An integrated circuit comprising: a terminal, an internal circuit, which generates a to-be outputted signal, and an output buffer, which receives said to-be-outputted signal from said internal circuit and, in response, drives said terminal to a voltage corresponding to a logic value of said to-be-outputted signal, said output buffer comprising: a first driver for driving said terminal to said voltage corresponding to said logic value of said to-be-outputted signal, a second driver for driving said terminal to said same voltage as said first driver, when said to-be-outputted signal transitions in logic value, and enable circuitry, having at least one input, said enable circuitry responds to a transition in logic value of said to-be-outputted signal by, after a predetermined delay following a time at which said first driver begins to drive said terminal, enabling said second driver to drive said terminal, but only enabling said second driver to drive said terminal for a predetermined time period, each input of said enable circuitry, receiving the same signal as a corresponding input of said first driver.

Claim 12

An integrated circuit comprising: a terminal, an internal circuit, which generates a to-be outputted signal, and an output buffer, which receives said to-be-outputted signal from said internal circuit and, in response, drives said terminal to a voltage corresponding to a logic value of said to-be-outputted signal, said output buffer comprising: a first driver for driving said terminal to said voltage corresponding to said logic value of said to-be-outputted signal, a second driver for driving said terminal to said same voltage as said first driver, when said to-be-outputted signal transitions in logic value, and enable circuitry, having at least one input, said enable circuitry responds to a transition in logic value of said to-be-outputted signal by, after a predetermined delay following a time at which said first driver begins to drive said terminal, enabling said second driver to drive said terminal, but only enabling said second driver to drive said terminal for a predetermined time period, each input of said enable circuitry, receiving the same signal as a corresponding input of said first driver.

Claim 13

The output buffer of claim 1 wherein said enable circuitry is connected in a feed forward path of of said second driver, said second driver isolating said enable circuitry from said voltage of said terminal so that each signal generated by said enable circuitry is independent of said voltage of said terminal.

Claim 14

The integrated circuit of claim 9 wherein said enable circuitry is connected in a feed forward path of said second driver that said second driver isolating said enable circuitry from said voltage of said terminal so that each signal generated by said enable circuitry is independent of said voltage of said terminal.

Claim 15

An output buffer comprising: a terminal, a first driver for driving said terminal to a voltage corresponding to a logic value of a to-be-outputted signal, a second driver for driving said terminal to said same voltage as said first driver, when said to-be-outputted signal transitions in logic value, and enable circuitry, which responds to a transition in logic value of said to-be-outputted signal by, after a predetermined delay, enabling said second driver to drive said terminal, but only enabling said second driver to drive said terminal for a predetermined time period said enable circuitry comprising: at least one delay element, which receives said to-be-outputted signal and which outputs at least one delayed output signal, after said predetermined delay, and a memory, which responds to said at least one delayed output signal outputted by said at least one delay element, by outputting at least one previously stored enabling value, for said predetermined time period, and by outputting at least one newly stored disabling value thereafter, said at least one previously stored enabling value enabling said second driver to drive said terminal and said at least one newly stored disabling value preventing said second driver from driving said terminal.

Claim 16

An output buffer comprising: a terminal, a first driver for driving said terminal to a voltage corresponding to a logic value of a to-be-outputted signal, a second driver for driving said terminal to said same voltage as said first driver, when said to-be-outputted signal transitions in logic value, and enable circuitry, which responds to a transition in logic value of said to-be-outputted signal by, after a predetermined delay, enabling said second driver to drive said terminal, but only enabling said second driver to drive said terminal for a predetermined time period said enable circuitry comprising: at least one delay element, which receives said to-be-outputted signal and which outputs at least one delayed output signal, after said predetermined delay, and a memory, which responds to said at least one delayed output signal outputted by said at least one delay element, by outputting at least one previously stored enabling value, for said predetermined time period, and by outputting at least one newly stored disabling value thereafter, said at least one previously stored enabling value enabling said second driver to drive said terminal and said at least one newly stored disabling value preventing said second driver from driving said terminal.

Claim 17

The output buffer of claim 12 wherein said enable circuitry further comprises: logic circuitry which responds to said at least one delayed output signal and said at least one previously stored enabling value by enabling said second driver to drive said terminal to a first voltage, when said to-be-outputted signal transitions to a first logic value corresponding to said first voltage, and for enabling said second driver to output a second voltage, when said to-be-outputted signal transitions to a second logic value corresponding to said second voltage.

Claim 18

The output buffer of claim 12 wherein said memory comprises: a first logic gate, receiving as a first input, at least one of said at least one delayed output signals from at least one of said at least one delay elements, a second logic gate, receiving as a first input, at least one of said at least one delayed output signals from at least one of said at least one delay elements, a second delay element connected between an output of said first logic gate and a second input of said second logic gate, and a third delay element connected between an output of said second logic gate and a second input of said first logic gate.