High-speed dual-buffered output circuit

Claim 2

An output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input to an input terminal thereof, said output circuit comprising: an output buffer, which is connected to the input and the output terminals and which, when activated, is capable of operating with, selectively, one of a high driving ability and a low driving ability; means for generating a control signal when the input signal is input; and activation means for activating said output buffer to operate with the high driving ability for a selected period in response to said control signal and, after the selected period, with the low driving ability.

Claim 3

An output circuit according to claim 1, wherein: the output circuit is included in a synchronous-type memory device which inputs a clock signal, the clock signal providing the control signal; and said activation means and said connection means operate in accordance with a signal level of the clock signal.

Claim 4

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input to an input terminal thereof, said output circuit comprising: a first output buffer which is operatively connected to the input and the output terminals; a second output buffer which has a driving ability higher than a driving ability of said first output buffer and is operatively connected to the input terminal; means for generating a control signal during a predetermined period immediately after the input signal is input; and connection means for selectively connecting the output terminal to said second output buffer for the predetermined period in response to said control signal and in accordance with a signal level of the clock signal being high or low.

Claim 5

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input to an input terminal thereof, said output circuit comprising: a first output buffer which is operatively connected to the input and the output terminals; a second output buffer which has a driving ability higher than a driving ability of said first output buffer and is operatively connected to the input terminal; means for generating a control signal during a predetermined period immediately after the input signal is input; and connection means for selectively connecting the output terminal to said second output buffer for the predetermined period in response to said control signal and in accordance with a signal level of the clock signal being high or low.

Claim 6

An output circuit according to claim 3, wherein: the clock signal provides the control signal.

Claim 7

An output circuit for driving a load connected to an output terminal thereof in accordance with an input signal having positive-logic and negative-logic input signals, the input signals applied to an input terminal thereof, said output circuit comprising: a clock signal providing a control signal during a predetermined period after the input signal is input; a first output buffer operatively connected to the input and output terminals having first and second transistors connected in series between first and second power sources with a midpoint between said first and said second transistors as an output thereof, said first and said second transistors being responsive to the positive-logic and the negative-logic input signals, respectively; a second output buffer connected in parallel to said first output buffer and, when activated, operates with a driving ability higher than said first output buffer, said second output buffer having third and fourth transistors connected in series between the first and the second power sources with a midpoint between said third and said fourth transistors as an output thereof, said third and said fourth transistors each having ohmic resistance smaller than said first and said second transistors; activation means for selectively activating said second output buffer for the predetermined period in response to the control signal, said activation means having a fifth and sixth transistors, said fifth transistor being responsive to the clock signal and the positive-logic input signal and said sixth transistor being responsive to the clock signal and the negative-logic input signal; and said third and said fourth transistors being responsive to said fifth and said sixth transistors, respectively.

Claim 8

An output circuit for driving a load connected to an output terminal thereof in accordance with an input signal having positive-logic and negative-logic input signals, the input signals applied to an input terminal thereof, said output circuit comprising: a clock signal providing a control signal during a predetermined period after the input signal is input; a first output buffer operatively connected to the input and output terminals having first and second transistors connected in series between first and second power sources with a midpoint between said first and said second transistors as an output thereof, said first and said second transistors being responsive to the positive-logic and the negative-logic input signals, respectively; a second output buffer connected in parallel to said first output buffer and, when activated, operates with a driving ability higher than said first output buffer, said second output buffer having third and fourth transistors connected in series between the first and the second power sources with a midpoint between said third and said fourth transistors as an output thereof, said third and said fourth transistors each having ohmic resistance smaller than said first and said second transistors; activation means for selectively activating said second output buffer for the predetermined period in response to the control signal, said activation means having a fifth and sixth transistors, said fifth transistor being responsive to the clock signal and the positive-logic input signal and said sixth transistor being responsive to the clock signal and the negative-logic input signal; and said third and said fourth transistors being responsive to said fifth and said sixth transistors, respectively.

Claim 9

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input applied to an input terminal thereof, said output circuit comprising: a first output buffer which is operatively connected to the input and the output terminals; a second output buffer which is connected in parallel to said first output buffer and, when activated, operates with driving ability higher than said first output buffer; the clock signal providing a control signal during a predetermined period after the input signal is input; and activation means for selectively activating said second output buffer for the predetermined period in accordance with a signal level of the clock signal being high or low.

Claim 10

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input applied to an input terminal thereof, said output circuit comprising: a first output buffer which is operatively connected to the input and the output terminals; a second output buffer which is connected in parallel to said first output buffer and, when activated, operates with driving ability higher than said first output buffer; the clock signal providing a control signal during a predetermined period after the input signal is input; and activation means for selectively activating said second output buffer for the predetermined period in accordance with a signal level of the clock signal being high or low.

Claim 11

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input to an input terminal thereof, said output circuit comprising: a first output buffer which is operatively connected to the output terminal; a second output buffer which has driving ability higher than said first output buffer and is operatively connected to the input terminal; and connection means operating in accordance with a signal level of the clock signal being high or low for operatively connecting the output terminal to said second output buffer for a predetermined period when the input signal is input and, after the period, to said first output buffer.

Claim 12

An output circuit for use in a synchronous-type memory device which inputs a clock signal, the output circuit for driving a load connected to an output terminal thereof in accordance with an input signal input to an input terminal thereof, said output circuit comprising: a first output buffer which is operatively connected to the output terminal; a second output buffer which has driving ability higher than said first output buffer and is operatively connected to the input terminal; and connection means operating in accordance with a signal level of the clock signal being high or low for operatively connecting the output terminal to said second output buffer for a predetermined period when the input signal is input and, after the period, to said first output buffer.